Datasheet

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB List of figures
Doc ID 16455 Rev 7 7/88
List of figures
Figure 1. STM32F100xx value line block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32F100xx value line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. STM32F100xx value line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. STM32F100xx value line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6. STM32F100xx value line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Maximum current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 38
Figure 13. Maximum current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 38
Figure 14. Typical current consumption on V
BAT
with RTC on vs. temperature at different V
BAT
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at V
DD
= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at V
DD
= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 17. Typical current consumption in Standby mode versus temperature at V
DD
= 3.3 V and
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 19. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 22. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 23. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 24. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 25. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 28. I
2
C bus AC waveforms and measurement circuit
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 30. SPI timing diagram - slave mode and CPHA = 1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 31. SPI timing diagram - master mode
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 32. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 33. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 34. Power supply and reference decoupling (V
REF+
not connected to V
DDA
). . . . . . . . . . . . . . 71
Figure 35. Power supply and reference decoupling (V
REF+
connected to V
DDA
). . . . . . . . . . . . . . . . . 71
Figure 36. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 37. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 76
Figure 38. Recommended footprint
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 77
Figure 40. Recommended footprint
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 41. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 78
Figure 42. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 79