Datasheet

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Description
Doc ID 16455 Rev 7 15/88
2.2.6 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 18 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
2.2.7 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 24 MHz.
2.2.8 Boot modes
At startup, boot pins are used to select one of three boot options:
● Boot from user Flash
● Boot from system memory
● Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.2.9 Power supply schemes
● V
DD
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through V
DD
pins.
● V
SSA
, V
DDA
= 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL (minimum voltage to be applied to V
DDA
is 2.4 V when the ADC or DAC is
used).
V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
● V
BAT
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V
DD
is not present.
2.2.10 Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
DD
is below a specified threshold, V
POR/PDR
, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD
/V
DDA
power supply and compares it to the V
PVD
threshold. An interrupt can be
generated when V
DD
/V
DDA
drops below the V
PVD
threshold and/or when V
DD
/V
DDA
is higher