Datasheet

Pinouts and pin description STM32F051x
28/30 Doc ID 018746 Rev 2
49 37 24
PA 14
(SWCLK)
I/O FT
(3)
USART2_TX, SWCLK
50 38 25 PA15 I/O FT
SPI1_NSS/I2S1_WS,
USART2_RX, TIM2_CH_ETR,
EVENTOUT
51 PC10 I/O FT
52 PC11 I/O FT
53 PC12 I/O FT
54 PD2 I/O FT TIM3_ETR
55 39 26 PB3 I/O FT
SPI1_SCK/I2S1_CK,
TIM2_CH2, TSC_G5_IO1,
EVENTOUT
56 40 27 PB4 I/O FT
SPI1_MISO/I2S1_MCK,
TIM3_CH1, TSC_G5_IO2,
EVENTOUT
57 41 28 PB5 I/O FT
SPI1_MOSI/I2S1_SD,
I2C1_SMBA, TIM16_BKIN,
TIM3_CH2
58 42 29 PB6 I/O FTf
I2C1_SCL, USART1_TX,
TIM16_CH1N, TSC_G5_IO3
59 43 30 PB7 I/O FTf
I2C1_SDA, USART1_RX,
TIM17_CH1N, TSC_G5_IO4
60 44 31 BOOT0 I B Boot memory selection
61 45 32 PB8 I/O FTf
I2C1_SCL, CEC, TIM16_CH1,
TSC_SYNC
62 46 PB9 I/O FTf
I2C1_SDA, IR_OUT,
TIM17_CH1, EVENTOUT
63 47 0 VSS S Digital ground
64 48 1 VDD S Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as a current sources (e.g. to drive an LED).
2. After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the reference manual.
3. After reset, these pins are configured as SWDAT and SWCLK alternate functions, and the internal pull-up on SWDAT pin
and internal pull-down on SWCLK pin are activated.
Table 11. Pin definitions (continued)
Pin number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64 LQFP48
UFQFPN32
Alternate functions Additional functions