Datasheet

Functional overview STM32F051x
18/22 Doc ID 018746 Rev 2
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interfaces can be served by the DMA controller.
Refer to Ta bl e 5 for the differences between I2C1 and I2C2.
3.14 Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds up to two universal synchronous/asynchronous receiver transmitters
(USART1 and USART2), which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. The USART1 supports also SmartCard communication
(ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has a
clock domain independent from the CPU clock, allowing the USART1 to wake up the MCU
from Stop mode.
The USART interfaces can be served by the DMA controller.Serial peripheral interface
(SPI).
Refer to Ta bl e 6 for the differences between USART1 and USART2.
Table 5. STM32F051xx I
2
C implementation
I2C features
(1)
1. X = supported.
I2C1 I2C2
7-bit addressing mode
XX
10-bit addressing mode
XX
Standard mode (up to 100 kbit/s)
XX
Fast mode (up to 400 kbit/s)
XX
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
Independent clock
X
SMBus
X
Wakeup from STOP
X