Datasheet

Functional overview STM32F051x
12/22 Doc ID 018746 Rev 2
3.7 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
3.8 Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
● Boot from User Flash
● Boot from System Memory
● Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
3.9 Power management
3.9.1 Power supply schemes
● V
DD
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through V
DD
pins.
● V
DDA
= 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL
(minimum voltage to be applied to V
DDA
is 2.4 V when the ADC and DAC are used).
The V
DDA
voltage level must be always greater or equal to the V
DD
voltage level and
must be provided first.
● V
BAT
= 1.6 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V
DD
is not present.
For more details on how to connect power pins, refer to Figure 9: Power supply scheme.
3.9.2 Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
POR/PDR
, without the need for an external reset circuit.
● The POR monitors only the V
DD
supply voltage. During the startup phase it is required
that V
DDA
should arrive first and be greater than or equal to V
DD
.
● The PDR monitors both the V
DD
and V
DDA
supply voltages, however the V
DDA
power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V
DDA
is higher than or
equal to V
DD
.