Datasheet

Electrical characteristics STM32F051x
90/105 Doc ID 022265 Rev 3
Table 67. I
2
S characteristics
Symbol Parameter Conditions Min Max Unit
f
CK
1/t
c(CK)
I
2
S clock frequency
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
1.597 1.601
MHz
Slave mode 0 6.5
t
r(CK)
I
2
S clock rise time
Capacitive load C
L
=15pF
-10
ns
t
f(CK)
I
2
S clock fall time - 12
t
w(CKH)
(1)
I2S clock high time
Master f
PCLK
= 16 MHz, audio
frequency = 48 kHz
306 -
t
w(CKL)
(1)
I2S clock low time 312 -
t
v(WS)
(1)
WS valid time Master mode 2 -
t
h(WS)
(1)
WS hold time Master mode 2 -
t
su(WS)
(1)
WS setup time Slave mode 7 -
t
h(WS)
(1)
WS hold time Slave mode 0 -
DuCy(SCK)
I2S slave input clock duty
cycle
Slave mode 25 75 %
t
su(SD_MR)
(1)
Data input setup time Master receiver 6 -
ns
t
su(SD_SR)
(1)
Data input setup time Slave receiver 2 -
t
h(SD_MR)
(1)(2)
Data input hold time
Master receiver 4 -
t
h(SD_SR)
(1)(2)
Slave receiver 0.5 -
t
v(SD_ST)
(1)(2)
Data output valid time
Slave transmitter (after enable
edge)
-20
t
h(SD_ST)
(1)
Data output hold time
Slave transmitter (after enable
edge)
13 -
t
v(SD_MT)
(1)(2)
Data output valid time
Master transmitter (after enable
edge)
- 4
t
h(SD_MT)
(1)
Data output hold time
Master transmitter (after enable
edge)
0-
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on f
PCLK
. For example, if f
PCLK
=8 MHz, then T
PCLK
= 1/f
PLCLK
=125 ns.