Datasheet

Electrical characteristics STM32F051x
86/105 Doc ID 022265 Rev 3
6.3.21 Communication interfaces
I
2
C interface characteristics
Unless otherwise specified, the parameters given in Ta bl e 6 4 are derived from tests
performed under ambient temperature, f
PCLK
frequency and V
DD
supply voltage conditions
summarized in Table 2 0 .
The I
2
C interface meets the requirements of the standard I
2
C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and V
DD
is
disabled, but is still present.
The I
2
C characteristics are described in Ta ble 6 4. Refer also to Section 6.3.13: I/O port
characteristics
for more details on the input/output alternate function characteristics (SDA
and SCL)
.
Table 64. I
2
C characteristics
(1)
Symbol Parameter
Standard mode Fast mode Fast Mode Plus
Unit
Min Max Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 - 1.3 - 0.5 -
µs
t
w(SCLH)
SCL clock high time 4.0 - 0.6 - 0.26 -
t
su(SDA)
SDA setup time 250 - 100 - 50 -
ns
t
h(SDA)
SDA data hold time 0
(3)
3450
(2)
0
(3)
900
(2)
0
(4)
450
(2)
t
r(SDA)
t
r(SCL)
SDA and SCL rise time - 1000 - 300 - 120
t
f(SDA)
t
f(SCL)
SDA and SCL fall time - 300 - 300 - 120
t
h(STA)
Start condition hold time 4.0 - 0.6 - 0.26 -
µs
t
su(STA)
Repeated Start condition
setup time
4.7 - 0.6 - 0.26 -
t
su(STO)
Stop condition setup time 4.0 - 0.6 - 0.26 - μs
t
w(STO:STA)
Stop to Start condition time
(bus free)
4.7 - 1.3 - 0.5 - μs
C
b
Capacitive load for each bus
line
- 400 - 400 - 550 pF
1.
The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in
production.
2.
The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
3.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
4. The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.