Datasheet

STM32F051x Revision history
Doc ID 022265 Rev 3 103/105
9 Revision history
Table 74. Document revision history
Date Revision Changes
05-Apr-2012 1 Initial release
25-Apr-2012 2
Updated Table 2: STM32F051x family device features and
peripheral counts for 1 SPI and 1 I2C in 32-pin package
Corrected Group 3 pin order in Table 5: Capacitive sensing
GPIOs available on STM32F051x devices.
Updated current consumptionTa bl e 2 5 to Ta bl e 2 9.
Updated Table 39: HSI14 oscillator characteristics
23-Jul-2012 3
Features reorganized and Section 3: Functional overview
structure changed.
Added LQFP32 package.
Updated Section 3.4: Cyclic redundancy check calculation
unit (CRC).
Modified number of priority levels in Section 3.9.1: Nested
vectored interrupt controller (NVIC).
Added note 3. for PB2 and PB8, changed TIM2_CH_ETR into
TIM2_CH1_ETR in Table 13: Pin definitions and Table 14:
Alternate functions selected through GPIOA_AFR registers
for port A. Added Table 15: Alternate functions selected
through GPIOA_AFR registers for port B.
Updated I
VDD
, I
VSS
, and I
INJ(PIN)
in Table 18: Current
characteristics .
Updated ACC
HSI
in Table 38: HSI oscillator characteristics
and Table 39: HSI14 oscillator characteristics.
Updated Table 49: I/O current injection susceptibility.
Added BOOT0 input low and high level voltage in Tabl e 5 0:
I/O static characteristics.
Modified number of pins in V
OL
and V
OH
description, and
changed condition for V
OLFM+
in Table 51: Output voltage
characteristics.
Changed V
DD
to V
DDA
in Figure 23: Typical connection
diagram using the ADC.
Updated Ts_temp in Table 59: TS characteristics.