Datasheet

STLVD111 Electrical characteristics
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Note: 1 All currents into device pins are positive; all currents out of device pins are negative. All
voltages are referenced to device ground unless otherwise specified
2 All typical values are given for V
CC
= 2.5V and T
A
= 25°C unless otherwise stated
Table 7. Driver electrical characteristics (T
A
= -40 to 85 °C, V
CC
= 2.5V ± 5%, unless otherwise
specified Note: 1, 2)
Symbol Parameter Test condition Min. Typ. Max. Unit
V
BB
Output reference voltage V
CC
= 2.5 V 1.15 1.25 1.35 V
I
CCD
Power supply current All driver enabled and loaded 125 160 mA
C
IN
Input capacitance V
I
= 0V to V
CC
5pF
C
OUT
Output capacitance 5 pF
V
IH
Logic input high threshold V
CC
= 2.5 V 2 V
V
IL
Logic input low threshold V
CC
= 2.5 V 0.8 V
I
I
Logic input current V
CC
= 2.5 V, V
IN
= V
CC
or GND ±10 µA
Table 8. LVDS timing characteristics (T
A
= -40 to 85 °C, V
CC
= 2.5V ± 5%, unless otherwise
specified)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
TLH,
t
THL
Transition time
R
L
= 100 Ω, C
L
= 5 pF,
Figure 7., Figure 8.)
220 300 ps
t
PHL,
t
PLH
Propagation delay time (Figure 7., Figure 8.)22.5ns
f
MAX
Maximum input frequency 700 900 MHz
t
SKEW
Bank skew (Figure 3.)50
psPart to part skew (Figure 4.) 100
Pulse skew (Figure 5.)50
Table 9. Control register timing characteristics (T
A
= -40 to 85 °C, V
CC
= 2.5V ± 5%, unless
otherwise specified)
Symbol Parameter Test condition Min. Typ. Max. Unit
f
MAX
Maximum frequency of shift register (Figure 9.) 100 150 MHz
t
s
Clock to SI setup time (Figure 9.)2ns
t
h
Clock to SI hold time (Figure 9.)1.5ns
t
rem
Enable to clock removal time (Figure 9.)1.5ns
t
W
Minimum clock pulse width (Figure 9.)3 ns