Datasheet

May 2007 Rev. 8 1/19
19
STLVD111
Programmable low voltage
1:10 differential LVDS clock driver
Features
100ps part-to part skew
50ps bank skew
Differential design
Meets LVDS spec. for driver outputs and
receiver inputs
Reference voltage available output V
BB
Low voltage V
CC
range of 2.375V to 2.625V
High signalling rate capability (exceeds
622MHz)
Support open, short and terminated input fail-
safe (low output state)
Programmable drivers power off control
Description
The STLVD111 is a low skew programmable 1 to
10 differential LVDS driver, designed for clock
distribution. The select signal is fanned out to 10
identical differential outputs.
The STLVD111 is provided with a 11 bit shift
register with a serial in and a Control Register.
The purpose is to enable or power off each output
clock channel and to select the clock input. The
STLVD111 is specifically designed, modelled and
produced with low skew as the key goal. Optimal
design and layout serve to minimize gate to gate
skew within a device. The net result is a
dependable guaranteed low skew device.
The STLVD111 can be used for high performance
clock distribution in 2.5V systems with LVDS
levels. Designers can take advantage of the
device’s performance to distribute low skew
clocks across the backplane or the board.
TQFP32
www.st.com
Order codes
Part number
Temperature
range
Package Packaging
STLVD111BFR -40 to 85 °C TQFP32 (Tape & Reel) 2400 parts per reel

Summary of content (19 pages)