Datasheet

STLM75 Functional description
Doc ID 13296 Rev 12 25/40
3.6 WRITE mode
In this mode the master transmitter transmits to the STLM75 slave receiver. Bus protocol is
shown in Figure 12. Following the START condition and slave address, a logic '0' (R/W
= 0)
is placed on the bus and indicates to the addressed device that word address will follow and
is to be written to the on-chip address pointer.
These modes are shown in the WRITE mode typical timing diagrams (see Figure 12, and
Figure 13, and Figure 14).
Figure 12. Typical pointer set followed by an immediate READ from the
configuration register
Figure 13. Configuration register WRITE
AI12230
1919
Repeat
Start
by
Master
ACK
by
STLM75
No ACK
by
STLM75
Stop
Cond.
by
Master
1 0 0 1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W
Address Byte Data Byte
1199
1
Start
by
Master
Address Byte
Pointer Byte
ACK
by
STLM75
ACK
by
STLM75
0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 D1 D0
AI12231
119919
1
Start
by
Master
Address Byte
Pointer Byte
ACK
by
STLM75
ACK
by
STLM75
ACK
by
STLM75
Stop
Cond.
by
Master
0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 0 0 0 D4 D3 D2 D1 D0D1 D0
Configuration Byte