Datasheet
Circuit description AN4164
8/38 Doc ID 023660 Rev 1
2 Circuit description
The power supply is set in flyback topology. The schematic is given in
Figure 2
, and the bill
of material in
Ta ble 2
. The input section includes a resistor R0 for inrush current limiting, a
diode bridge (D0) and a Pi filter for EMC suppression (Cin1, Lin, Cin2). The transformer core
is a standard E13. The output voltage value is set in a simple way through the RfbH-RfbL
voltage divider between the output terminal and the FB pin, according to the following
formula:
Equation 1
In fact, the FB pin is the input of an error amplifier and is an accurate 3.3 V voltage
reference. In the schematic the upper resistor RfbH has been split into RfbH1 and RfbH2;
and the lower resistor RfbL into RfbL1 and RfbL2 in order to allow a better tuning of the
output voltage value. The compensation network is connected between the COMP pin
(which is the output of the error amplifier) and the GND pin, and is made up of Cp, Cc and
Rc.
The resistor RLIM, placed between the LIM and GND pins, has the purpose of reducing the
drain current limitation, from IDLIM to about 250 mA in order to limit the deliverable output
power of the converter and keep safe the power components. At power-up, as the rectified
input voltage rises over the V
DRAINSTART
threshold, the high voltage current generator starts
charging the V
DD
capacitor, CVDD, from 0 V up to V
DDon
. At this point the Power MOSFET
starts switching, the HV current generator is turned off and the IC is biased by the energy
stored in CVDD.
In this demonstration board, if the jumper J1 is not selected, the IC is biased through the
internal high-voltage startup current generator, which is automatically turned on as the V
DD
voltage drops down to V
DDCSon
and switched off as V
DD
is charged up to V
DDon
(self-
biasing).
Self-biasing is excluded by keeping the V
DD
pin voltage always above the V
DD
CSon
threshold.
In this board, since the output voltage is higher than V
DDCSon
, this is obtained by just
selecting the jumper J1, which connects the output terminal to the V
DD
pin through a small
signal diode. If the output voltage is lower than V
DDCSon
, the self-biasing can be excluded
only using an auxiliary winding. The IC biasing through auxiliary winding or through the
output is referred to as external biasing. In
Figure 3
the V
DD
waveforms for both cases (IC
external biased and self-biased) are shown.
The use of self-biasing means higher power dissipation across the IC (which must be
avoided if low standby consumption and/or high efficiency is required) and higher IC
temperature respect to external biasing (at given ambient temperature, the maximum
deliverable output power is lower; or, a lower maximum ambient temperature is required to
deliver the same power throughput).
For this reason, two different maximum T
AMB
values, in full load condition, are indicated in
Table 1
, depending on the selection of weather self biasing or external biasing. These
values are confirmed by the thermal measurements reported in
Section 8
.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+⋅=
RfbL
RfbH
VV
OUT 13.3