Datasheet

AN4164 Testing the board
Doc ID 023660 Rev 1 13/38
5.2 Line/load regulation and output voltage ripple
The output voltage of the board has been measured in different line and load conditions.
The results are shown in
Ta ble 4 . The output voltage is practically not affected by the line
condition and by the IC biasing (self-biasing or external biasing).
Table 4. Output voltage line-load regulation
V
IN
[V
AC
]
V
OUT
[V]
No load 50% load 75% load 100% load
IC externally
biased
IC self
biased
IC externally
biased
IC self
biased
IC externally
biased
IC self
biased
IC externally
biased
IC self
biased
90 12.04 12.05 12.00 11.98 12.00 11.98 11.99 11.97
115 12.05 12.05 12.00 11.99 12.00 11.98 11.99 11.97
150 12.05 12.05 12.00 11.98 12.00 11.98 11.99 11.97
180 12.05 12.04 12.00 11.98 12.00 11.98 11.99 11.97
230 12.05 12.04 12.00 11.98 12.00 11.98 11.99 11.97
265 12.05 12.04 12.00 11.98 12.00 11.98 11.99 11.97
Figure 13. Line regulation, IC externally
biased (J1 selected)
Figure 14. Line regulation, IC self-biased
(J1 not selected)
AM11688v1
11.7
11.8
11.9
12
12.1
12.2
80 105 130 155 180205230 255
V
OUT
[V]
V
IN
[V
AC
]
0
25%
50%
75%
100%
AM11689v1
11.7
11.8
11.9
12
12.1
12.2
80 105 130 155 180205230 255
V
OUT
[V]
V
IN
[V
AC
]
0
25%
50%
75%
100%
Figure 15. Load regulation, IC externally
biased (J1 selected)
Figure 16. Load regulation, IC self-biased
(J1 not selected)
AM11690v1
11.7
11.8
11.9
12
12.1
12.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.350.4
V
OUT
[V]
I
OUT
[A]
90
115
230
265
AM11691v1
11.7
11.8
11.9
12
12.1
12.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
V
OUT
[V]
I
OUT
[A]
90
115
230
265