Datasheet

Electrical specifications HVLED815PF
12/36 Doc ID 023409 Rev 4
Figure 5. OFF-state drain and source current test circuit
Note: The measured IDSS is the sum between the current across the startup resistor and the
effective
MOSFET’s OFF-state drain current.
I
COMP
Source current
V
DMG
= 2.3 V,
V
COMP
= 1.65 V
70 100 µA
Sink current
V
DMG
= 2.7 V,
V
COMP
= 1.65 V
400 750 µA
V
COMPH
Upper COMP voltage V
DMG
= 2.3 V 2.7 V
V
COMPL
Lower COMP voltage V
DMG
= 2.7 V 0.7 V
V
COMPBM
Burst-mode threshold 1 V
Hys Burst-mode hysteresis 65 mV
Current reference
V
ILEDx
Maximum value V
COMP
= V
COMPL
1.5 1.6 1.7 V
V
CLED
Current reference voltage 0.192 0.2 0.208 V
Current sense
t
LEB
Leading-edge blanking
(5)
330 ns
T
D
Delay-to-output (H-L) 90 200 ns
V
CSx
Max. clamp value
(4)
dVcs/dt = 200 mV/µs 0.7 0.75 0.8 V
V
CSdis
Hiccup-mode OCP level
(4)
0.92 1 1.08 V
1. V
CC
=14 V (unless otherwise specified).
2. Limits are production tested at Tj=Ta=25 °C, and are guaranteed by statistical characterization in the range
Tj -25 to +125
°C.
3. Not production tested, guaranteed statistical characterization only.
4. Parameters tracking each other (in the same section).
5. Guaranteed by design.
Table 5. Electrical characteristics
(1) (2)
(continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
2.5V
COMP SOURCE
DRAIN
VDD
+
-
CURR ENT
CONTROL
ILED
GND
DMG
CS
Vin
750V
A
Idss
14V
AM13211v1