Datasheet

DocID023755 Rev 4 25/31
STC3115 I
2
C interface
31
Table 14. REG_CTRL - address 1
Name Position Type Def. Description
IO0DATA 0
RX
ALM pin status
0 = ALM input is low
1 = ALM input is high
W1
ALM pin output drive
0 = ALM is forced low
1 = ALM is driven by the alarm conditions
GG_RST 1 W 0
0: no effect
1: resets the conversion counter
GG_RST is a self-clearing bit.
GG_VM 2 R 0
Voltage mode active
0 = REG_SOC from Coulomb counter mode
1 = REG_SOC from Voltage mode
BATFAIL 3 R/W 0
Battery removal or UVLO detection bit.
Write 0 to clear
(Write 1 is ignored)
PORDET 4
R1
Power on reset (POR) detection bit
0 = no POR event occurred
1 = POR event occurred
W0
Soft reset
0 = release the soft-reset and clear the POR
detection bit,
1 = assert the soft-reset and set the POR detection
bit.
This bit is self clearing.
ALM_SOC 5 R/W 0
Set with a low-SOC condition.
Cleared by writing 0.
ALM_VOLT 6 R/W 0
Set with a low-voltage condition.
Cleared by writing 0.
7 Unused