Datasheet

I
2
C interface STC3115
20/31 DocID023755 Rev 4
7 I
2
C interface
7.1 Read and write operations
The I
2
C interface is used to control and read the current accumulator and registers. It is
compatible with the Philips I
2
C Bus® (version 2.1). It is a slave serial interface with a serial
data line (SDA) and a serial clock line (SCL).
• SCL: input clock used to shift data
• SDA: input/output bidirectional data transfers
A filter rejects the potential spikes on the bus data line to preserve data integrity.
The bidirectional data line supports transfers up to 400 Kbit/s (fast mode). The data are
shifted to and from the chip on the SDA line, MSB first.
The first bit must be high (START) followed by the 7-bit device address and the read/write
control bit. Bits DevADDR0 to DevADDR2 are factory-programmable, the default device
address value being 1110 000 (AddrID0 = AddrID1 = AddrID2 = 0). The STC3115 then
sends an acknowledge at the end of an 8-bit long sequence. The next eight bits correspond
to the register address followed by another acknowledge.
The data field is the last 8-bit long sequence sent, followed by a last acknowledge.
Table 9. Device address format
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
1110DevADDR2 DevADDR1 DevADDR0 R/W
Table 10. Register address format
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
RegADDR7 RegADDR6 RegADDR5 RegADDR4 RegADDR3 RegADDR2 RegADDR1 RegADDR0
Table 11. Register data format
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0