Datasheet

STC3100 I2C interface
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Figure 8. Read operation
Figure 9. Write operation
Start Device addr Reg address
8 bits
A
Restart Device addr
A
Reg data
8 bits
A
Reg data
8 bits
A
Reg data
8 bits
A
Address
n+1
Start bit = SDA falling when SCL = 1
7 bits 7 bits
Stop
A
W
Stop bit = SDA rising when SCL = 1
Restart bit = start a
fter a start
Master
Slave
Acknowledge = SDA forced low during a SCL clock
R
Address
n+2
AM00833
Start Device addr Reg address
8 bits
A
Reg data
A
Reg data
8 bits
A
Reg data
8 bits
A
Address
n+1
Start bit = SDA falling when SCL = 1
7 bits8 bits
Stop
A
W
Stop bit = SDA rising when SCL = 1
Restart bit = start after a start
Address
n+2
AM00834