Datasheet

Register description STA559BW
52/67 Doc ID 18190 Rev 1
6.7 User-defined coefficient control registers (addr 0x16 - 0x26)
6.7.1 Coefficient address register (addr 0x16)
1001 -15
1010 -14
1011 -13
1100 -12
1101 -10
1110 -7
1111 -4
Table 70. Limiter release threshold vs LxRT bits (DRC mode)
LxRT[3:0] DRC (db relative to Volume + LxAT)
0000 -∞
0001 -38
0010 -36
0011 -33
0100 -31
0101 -30
0110 -28
0111 -26
1000 -24
1001 -22
1010 -20
1011 -18
1100 -15
1101 -12
1110 -9
1111 -6
Table 69. Limiter attack threshold vs LxAT bits (DRC mode) (continued)
LxAT[3:0] DRC (dB relative to Volume)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved Reserved CFA5 CFA4 CFA3 CFA2 CFA1 CFA0
00000000