Datasheet

STA559BW Register description
Doc ID 18190 Rev 1 43/67
6.3 Audio preset registers (addr 0x0B and 0x0C)
6.3.1 Audio preset register 1 (addr 0x0B)
Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured
to properly fit application specific configurations.
The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].
When this value is 00 then bits AMGC[1:0] are defined below in Tab l e 5 3 .
6.3.2 Audio preset register 2 (addr 0x0C)
AM interference frequency switching
D7 D6 D5 D4 D3 D2 D1 D0
Reserved Reserved AMGC[1] AMGC[0] Reserved Reserved Reserved Reserved
10000000
Table 53. Audio preset gain compression/limiters selection for AMGC[3:2] = 00
AMGC[1:0] Mode
00 User programmable GC
01 AC no clipping 2.1
10 AC limited clipping (10%) 2.1
11 DRC night-time listening mode 2.1
D7 D6 D5 D4 D3 D2 D1 D0
XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME
00000000
Table 54. AM interference frequency switching bits
Bit R/W RST Name Description
0 R/W 0 AMAME
Audio preset AM enable
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings
Table 55. Audio preset AM switching frequency selection
AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs
000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz
001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz
010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz
011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz
100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz