Datasheet

STA559BW Register description

Doc ID 18190 Rev 1 39/67

Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I

S data and automatically

mutes if the signals are perceived as invalid.

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

LRCK double trigger protection

LDTE, when enabled, prevents double trigger of LRCLK on instable I2S input.

Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

IC power down

Table 44. Invalid input detect mute enable

Bit R/W RST Name Description

2R/W1 IDE

0: disables the automatic invalid input detect mute

1: enables the automatic invalid input detect mute

Table 45. Binary output mode clock loss detection

Bit R/W RST Name Description

3R/W1 BCLE

0: binary output mode clock loss detection disabled

1: binary output mode clock loss detection enable

Table 46. LRCK double trigger protection

Bit R/W RST Name Description

4R/W1 LDTE

0: LRCLK double trigger protection disabled

1: LRCLK double trigger protection enabled

Table 47. Auto EAPD on clock loss

Bit R/W RST Name Description

5R/W0 ECLE

0: auto EAPD on clock loss not enabled

1: auto EAPD on clock loss

Table 48. IC power down

Bit R/W RST Name Description

6R/W1 PWDN

0: IC power down low-power condition

1: IC normal operation