Datasheet

Register description STA559BW
36/67 Doc ID 18190 Rev 1
2.0 channels, two full-bridges (OCFG = 00)
Mapping:
z FFX1A -> OUT1A
z FFX1B -> OUT1B
z FFX2A -> OUT2A
z FFX2B -> OUT2B
z FFX3A -> OUT3A
z FFX3B -> OUT3B
z FFX4A -> OUT4A
z FFX4B -> OUT4B
Default modulation:
z FFX1A/1B configured as ternary
z FFX2A/2B configured as ternary
z FFX3A/3B configured as lineout ternary
z FFX4A/4B configured as lineout ternary
On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On
channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this
configuration, volume control or EQ have no effect on channels 3 and 4.
In this configuration the PWM slot phase is the following as shown in Figure 14.
Figure 14. 2.0 channels (OCFG = 00) PWM slots
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B