Datasheet

STA559BW Register description
Doc ID 18190 Rev 1 27/67
To make the STA559BW work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock. It means that:
 N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles,
where N depends on the settings in Table 12 on page 23.
 the PLL must be locked.
If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the
STA559BW immediately mutes the I
2
S PCM data out (provided to the processing block) and
it freezes any active processing task.
Clock desyncronization can happen during STA559BW operation because of source
switching or TV channel change. To avoid audio side effects, like click or pop noise, it is
strongly recommended to complete the following actions:
1. soft volume change
2. I
2
C read /write instructions
while the serial audio interface and the internal PLL are still synchronous.
Delay serial clock enable
Channel input mapping
Each channel received via I
2
S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers maps each I
2
S input channel to its corresponding processing channel.
6.1.3 Configuration register C (addr 0x02)
FFX power output mode
The FFX power output mode selects how the FFX output timing is configured.
Different power devices use different output modes.
Table 20. Delay serial clock enable
Bit R/W RST Name Description
5 R/W 0 DSCKE
0: no serial clock delay
1: serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
2
S master devices
Table 21. Channel input mapping
Bit R/W RST Name Description
6R/W0 C1IM
0: processing channel 1 receives left I
2
S Input
1: processing channel 1 receives right I
2
S Input
7R/W1 C2IM
0: processing channel 2 receives left I
2
S Input
1: processing channel 2 receives right I
2
S Input
D7 D6 D5 D4 D3 D2 D1 D0
OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0
10010111