Datasheet

STA559BW Register description
Doc ID 18190 Rev 1 23/67
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (f
s
).
The relationship between the input clock and the input sample rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally.
Interpolation ratio select
The STA559BW has variable interpolation (oversampling) settings such that internal
processing and FFX output rates remain consistent. The first processing block interpolates
by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The
oversampling ratio of this interpolation is determined by the IR bits.
Table 10. Input sampling rates
Input sample rate
fs (kHz)
IR MCS[2:0]
101 100 011 010 001 000
32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
88.2, 96 01 NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs
176.4, 192 1X NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs
Table 11. Internal interpolation ratio
Bit R/W RST Name Description
4:3 R/W 00 IR [1:0]
Selects internal interpolation ratio based on input I
2
S
sample frequency
Table 12. IR bit settings as a function of input sample rate
Input sample rate fs (kHz) IR 1st stage interpolation ratio
32 00 2-times oversampling
44.1 00 2-times oversampling
48 00 2-times oversampling
88.2 01 Pass-through
96 01 Pass-through
176.4 10 2-times downsampling
192 10 2-times downsampling