Datasheet

Register description STA559BW
22/67 Doc ID 18190 Rev 1
6.1 Configuration registers (addr 0x00 to 0x05)
6.1.1 Configuration register A (addr 0x00)
Master clock select
The STA559BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
z 32.768 MHz for 32 kHz
z 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
z 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
0x1F A1CF3
C3B[7:0]
0x20 A2CF1
C4B[23:16]
0x21 A2CF2
C4B[15:8]
0x22 A2CF3
C4B[7:0]
0x23 B0CF1
C5B[23:16]
0x24 B0CF2
C5B[15:8]
0x25 B0CF3
C5B[7:0]
0x26 CFUD
Reserved RA R1 WA W1
0x27 MPCC1
MPCC[15:8]
0x28 MPCC2
MPCC[7:0]
0x29 DCC1
DCC[15:8]
0x2A DCC2
DCC[7:0]
0x2B FDRC1
FDRC[15:8]
0x2C FDRC2
FDRC[7:0]
0x2D STATUS
PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN
Table 8. Register summary (continued)
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0
01100011
Table 9. Master clock select
Bit R/W RST Name Description
0R/W1 MCS0
Selects the ratio between the input I
2
S sample
frequency and the input clock.
1R/W1 MCS1
2R/W0 MCS2