Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsLinear ICsLinear IC - Custom audio Pre-amp I²C, I²S PowerSSO 36

December 2010 Doc ID 18190 Rev 1 1/67

STA559BW

5-volt, 2-amp, 2.1-channel high-efficiency digital audio system

Sound Terminal®

Features

 Wide-range supply voltage, 4.5 V to 16 V

 Three power output configurations:

– 2 channels of ternary PWM

(2 x 3 W into 4 Ω at 5 V) + PWM output

– 2 channels of ternary PWM

(2 x 3 W into 4 Ω at 5 V) + ternary stereo

line-out

– 2.1 channels of binary PWM (left, right,

LFE) (2 x 0.7 W + 1 x 3 W into 4 Ω at 5 V)

(2 x 1.4 W + 1 x 6 W into 2 Ω at 5 V)

 FFX with 100-dB SNR and dynamic range

 Selectable 32- to 192-kHz input sample rates

 I

C control with selectable device address

 Digital gain/attenuation +48 dB to -80 dB with

0.5-dB/step resolution

 Soft volume update

 Individual channel and master gain/attenuation

 Two independent limiters/compressors

 Dynamic range compression or anti-clipping

modes

 Audio presets:

– 15 preset crossover filters

– 5 preset anti-clipping modes

– Preset night-time listening mode

 Individual channel soft/hard mute

 Independent channel volume and DSP bypass

 2-channel I

S input data interface

 Input and output channel mapping

 Automatic invalid-input detect Mute

 Automatic zero-detect mute

 Up to 4 user-programmable biquads/channel

 Three coefficients banks for EQ presets storing

with fast recall via I

C interface

 Bass/treble tones and de-emphasis control

 Selectable high-pass filter for DC blocking

 Advanced AM interference frequency

switching and noise suppression modes

 Selectable high- or low-bandwidth

noise-shaping topologies

 Selectable clock input ratio

 Thermal overload and short-circuit protection

embedded

 Video apps: 576 x f

input mode supported

Table 1. Device summary

Order code Package Packaging

STA559BW PowerSSO-36 EPD Tube

STA559BWTR PowerSSO-36 EPD Tape and reel

PowerSSO-36

with exposed pad down (EPD)

www.st.com

Summary of content (67 pages)

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STA559BW 5-volt, 2-amp, 2.1-channel high-efficiency digital audio system Sound Terminal® Features Wide-range supply voltage, 4.5 V to 16 V Three power output configurations: – 2 channels of ternary PWM (2 x 3 W into 4 Ω at 5 V) + PWM output – 2 channels of ternary PWM (2 x 3 W into 4 Ω at 5 V) + ternary stereo line-out – 2.1 channels of binary PWM (left, right, LFE) (2 x 0.7 W + 1 x 3 W into 4 Ω at 5 V) (2 x 1.
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Contents STA559BW Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STA559BW Contents 6.1 6.2 6.3 Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . .
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Contents STA559BW 6.11 7 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2 PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3 Typical output configuration . . . . . .
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STA559BW List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of tables STA559BW List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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STA559BW Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. List of tables External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Description 1 STA559BW Description The STA559BW is an integrated solution of digital audio processing, digital amplifier controls and power output stage to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The FFX processor implements the ternary, binary and binary differential processing capabilities of the full FFX processor.
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STA559BW Pin connections 2 Pin connections 2.1 Connection diagram Figure 2.
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Pin connections STA559BW Table 2. Pin description (continued) Pin 10/67 Type Name Description 11 Power VCC1 Power positive supply 12 GND GND1 Power negative supply 13 O OUT1A Output half-bridge channel 1A 14 GND GND_REG Internal ground reference 15 Power VDD Internal 3.
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STA559BW Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Typ Max Unit VCC Power supply voltage (pins VCCx) -0.3 - 24 V VDD Digital supply voltage (pins VDD_DIG) -0.3 - 4.0 V VDD PLL supply voltage (pin VDD_PLL) -0.3 - 4.0 V Top Operating junction temperature -20 - 150 °C Tstg Storage temperature -40 - 150 °C Warning: 3.
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Electrical specifications 3.3 STA559BW Recommended operating conditions Table 5. Recommended operating condition Symbol 3.4 Parameter Min Typ Max Unit VCC Power supply voltage (VCCxA, VCCxB) 4.5 - 16.0 V VDD_DIG Digital supply voltage 2.7 3.3 3.6 V VDD_PLL PLL supply voltage 2.7 3.3 3.6 V Tamb Ambient temperature -20 - 70 °C Electrical specifications for the digital section The specifications given in this section are valid for Tamb = 25 °C unless otherwise specified.
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STA559BW 3.5 Electrical specifications Electrical specifications for the power section The specifications given in this section are valid for the operating conditions: VCC = 5 V, f = 1 kHz, fsw = 384 kHz, Tamb = 25 °C and RL = 4 Ω, unless otherwise specified. Table 7. Electrical specifications - power section Symbol Parameter Conditions Output power BTL Po Output power SE Min Typ Max THD = 1%RL= 2 Ω - 4.2 - THD = 10%RL= 2 Ω - 5.3 - THD = 1%,RL= 2 Ω - 1 - THD = 10%,RL= 2 Ω - 1.
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Electrical specifications Figure 3.
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STA559BW 3.6 Electrical specifications Power on/off sequence Figure 4. Power-on sequence Note: no specific VCC and VDD_DIG turn−on sequence is required VCC Don’t care VDD_Dig XTI Don’t care Reset TC TR I2C Don’t care CMD0 CMD1 CMD2 PWDN TR = minimum time between XTI master clock stable and Reset removal: 1 ms TC = minimum time between Reset removal and I2C program, sequence start: 1ms Note: The definition of a stable clock is when fmax - fmin < 1 MHz.
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Processing data paths 4 STA559BW Processing data paths Figure 6 below shows the data processing paths inside STA559BW. The whole processing chain can be considered as two consecutive sections. In the first one, dual-channel processing is implemented and in the second section each channel is fed into the post mixing block, either to generate a third channel (typically used in 2.1 output configuration and with crossover filters enabled) or to have the channels processed by the dual-band DRC block (2.
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STA559BW Processing data paths Figure 6.
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I2C bus specification 5 STA559BW I2C bus specification The STA559BW supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization.
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I2C bus specification STA559BW 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA559BW acknowledges this and then waits for the byte of internal address. After receiving the internal byte address the STA559BW again responds with an acknowledgement. 5.3.1 Byte write In the byte write mode the master sends one data byte, this is acknowledged by the STA559BW. The master then terminates the transfer by generating a STOP condition. 5.3.
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I2C bus specification 5.4.4 STA559BW Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA559BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. Figure 8.
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STA559BW Register description 6 Register description Note: Addresses exceeding the maximum address number must not be written. Table 8.
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Register description Table 8.
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STA559BW Register description The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 10.
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Register description STA559BW Thermal warning recovery bypass Table 13. Bit Thermal warning recovery bypass R/W 5 R/W RST 1 Name Description 0: thermal warning recovery enabled 1: thermal warning recovery disabled TWRB This bit sets the behavior of the IC after a thermal warning disappears. If TWRB is enabled the device automatically restores the normal gain and output limiting is no longer active.
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STA559BW Register description Serial audio input interface format Table 16. Bit Serial audio input interface R/W RST Name 0 R/W 0 SAI0 1 R/W 0 SAI1 2 R/W 0 SAI2 3 R/W 0 SAI3 Description Determines the interface format of the input serial digital audio interface. Serial data interface The STA559BW audio serial input interfaces with standard digital audio components and accepts a number of serial data formats.
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Register description Table 18. STA559BW Support serial audio input formats for MSB-first (continued) BICKI SAI [3:0] SAIFB Interface format 2 0000 0 I S 16 to 24-bit data 0001 0 Left-justified 16 to 24-bit data 0010 0 Right-justified 24-bit data 0110 0 Right-justified 20-bit data 1010 0 Right-justified 18-bit data 1110 0 Right-justified 16-bit data 64 * fs Table 19.
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STA559BW Register description To make the STA559BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that: N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles, where N depends on the settings in Table 12 on page 23. the PLL must be locked.
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Register description STA559BW Table 22. Bit FFX power output mode R/W RST Name 0 R/W 1 OM0 1 R/W 1 OM1 Description Selects configuration of FFX output: 00: drop compensation 01: discrete output stage: tapered compensation 10: full-power mode 11: variable drop compensation (CSZx bits) FFX compensating pulse size register Table 23. Bit FFX compensating pulse size bits R/W RST Name 2 R/W 1 CSZ0 3 R/W 1 CSZ1 4 R/W 1 CSZ2 5 R/W 0 CSZ3 Table 24.
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STA559BW 6.1.4 Register description Configuration register D (addr 0x03) D7 D6 D5 D4 D3 D2 D1 D0 SME ZDE DRC BQL PSL DSPB DEMP HPB 0 1 0 0 0 0 0 0 High-pass filter bypass Table 26. Bit 0 High-pass filter bypass R/W R/W RST 0 Name HPB Description 1: bypass internal AC coupling digital high-pass filter The STA559BW features an internal digital high-pass filter for the purpose of AC coupling.
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Register description STA559BW Biquad coefficient link Table 30. Bit 4 Biquad coefficient link R/W R/W RST 0 Name Description 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values BQL For ease of use, all channels can use the biquad coefficients loaded into the Channel-1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. Dynamic range compression/anti-clipping bit Table 31.
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STA559BW 6.1.5 Register description Configuration register E (addr 0x04) D7 D6 D5 D4 D3 D2 D1 D0 SVE ZCE DCCV PWMS AME NSBW MPC MPCV 1 1 0 0 0 0 1 0 Max power correction variable Table 34. Bit 0 Max power correction variable R/W RST R/W 0 Name Description 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient MPCV Max power correction Table 35.
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Register description STA559BW PWM speed mode Table 38. Bit R/W 4 R/W PWM speed mode RST 0 Name Description 0: normal speed (384 kHz) all channels 1: odd speed (341.3 kHz) all channels PWMS Distortion compensation variable enable Table 39. Bit R/W 5 R/W Distortion compensation variable enable RST 0 Name Description 0: use preset DC coefficient 1: use DCC coefficient DCCV Zero-crossing volume enable Table 40.
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STA559BW Register description Output configuration Table 42. Bit Output configuration R/W RST Name 0 R/W 0 OCFG0 1 R/W 0 OCFG1 Description Selects the output configuration Table 43.
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Register description Figure 9. STA559BW OCFG = 00 (default value) Half Bridge OUT1A Channel 1 Half Bridge Half Bridge OUT1B OUT2A Channel 2 Half Bridge OUT2B OUT3A OUT3B LineOut1 LPF OUT4A OUT4B LineOut2 LPF Figure 10. OCFG = 01 Half Bridge Half Bridge Half Bridge Channel 1 OUT1A Channel 2 OUT1B OUT2A Channel 3 Half Bridge OUT2B Figure 11.
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STA559BW Register description Figure 12. OCFG = 11 OUT1A Half Bridge Half Bridge OUT1B Channel 3 Half Bridge Half Bridge OUT2A OUT2B OUT3A OUT3B Channel 1 OUT4A OUT4B Channel 2 The STA559BW can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length.
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Register description STA559BW 2.0 channels, two full-bridges (OCFG = 00) Mapping: z FFX1A -> OUT1A z FFX1B -> OUT1B z FFX2A -> OUT2A z FFX2B -> OUT2B z FFX3A -> OUT3A z FFX3B -> OUT3B z FFX4A -> OUT4A z FFX4B -> OUT4B Default modulation: z FFX1A/1B configured as ternary z FFX2A/2B configured as ternary z FFX3A/3B configured as lineout ternary z FFX4A/4B configured as lineout ternary On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent.
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STA559BW Register description 2.1 channels, two half-bridges + one full-bridge (OCFG = 01) Mapping: z FFX1A -> OUT1A z FFX2A -> OUT1B z FFX3A -> OUT2A z FFX3B -> OUT2B z FFX1A -> OUT3A z FFX1B -> OUT3B z FFX2A -> OUT4A z FFX2B -> OUT4B Modulation: z FFX1A/1B configured as binary z FFX2A/2B configured as binary z FFX3A/3B configured as binary z FFX4A/4B configured as binary In this configuration, channel 3 has full control (volume, EQ, etc…).
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Register description STA559BW 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) Mapping: z FFX1A -> OUT1A z FFX1B -> OUT1B z FFX2A -> OUT2A z FFX2B -> OUT2B z FFX3A -> OUT3A z FFX3B -> OUT3B z EAPD -> OUT4A z TWARN -> OUT4B Default modulation: z FFX1A/1B configured as ternary z FFX2A/2B configured as ternary z FFX3A/3B configured as ternary z FFX4A/4B is not used In this configuration, channel 3 has full control (volume, EQ, etc…).
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STA559BW Register description Invalid input detect mute enable Table 44. Bit 2 Invalid input detect mute enable R/W R/W RST 1 Name Description 0: disables the automatic invalid input detect mute 1: enables the automatic invalid input detect mute IDE Setting the IDE bit enables this function, which looks at the input I2S data and automatically mutes if the signals are perceived as invalid. Binary output mode clock loss detection Table 45.
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Register description STA559BW The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, then the master clock to all internal hardware expect the I2C block is gated. This places the IC in a very low power consumption state. External amplifier power down Table 49.
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STA559BW 6.2.1 Register description Mute/line output configuration register (addr 0x06) D7 D6 D5 D4 D3 D2 D1 D0 LOC1 LOC0 Reserved Reserved C3M C2M C1M Reserved 0 0 0 0 0 0 0 0 Table 50. Line output configuration LOC[1:0] Line output configuration 00 Line output fixed - no volume, no EQ 01 Line output variable - channel 3 volume effects line output, no EQ 10 Line output variable with EQ - channel 3 volume effects line output Line output is only active when OCFG = 00.
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Register description 6.2.5 STA559BW Channel 3 / line output volume (addr 0x0A) D7 D6 D5 D4 D3 D2 D1 D0 C3VOL7 C3VOL6 C3VOL5 C3VOL4 C3VOL3 C3VOL2 C3VOL1 C3VOL0 0 1 1 0 0 0 0 0 Table 52. Channel volume as a function of CxVOL CxVOL[7:0] 42/67 Volume 00000000 (0x00) +48 dB 00000001 (0x01) +47.5 dB 00000010 (0x02) +47 dB … … 01011111 (0x5F) +0.5 dB 01100000 (0x60) 0 dB 01100001 (0x61) -0.5 dB … … 11010111 (0xD7) -59.
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STA559BW Register description 6.3 Audio preset registers (addr 0x0B and 0x0C) 6.3.1 Audio preset register 1 (addr 0x0B) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved AMGC[1] AMGC[0] Reserved Reserved Reserved Reserved 1 0 0 0 0 0 0 0 Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].
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Register description STA559BW Table 55. Audio preset AM switching frequency selection (continued) AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs 101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz 110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz Bass management crossover Table 56. Bit Bass management crossover R/W RST Name 4 R/W 0 XO0 5 R/W 0 XO1 6 R/W 0 XO2 7 R/W 0 XO3 Table 57. Selects the bass-management crossover frequency.
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STA559BW 6.
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Register description STA559BW Binary output enable registers Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is negative inverse. Table 61. Binary output enable registers CxBO Mode 0 FFX output operation 1 Binary output Limiter select Limiter selection can be made on a per-channel basis according to the channel limiter select bits. . Table 62.
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STA559BW 6.5 Register description Tone control register (addr 0x11) D7 D6 D5 D4 D3 D2 D1 D0 TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 0 1 1 1 0 1 1 1 Tone control Table 64. Tone control boost/cut as a function of BTC and TTC bits BTC[3:0]/TTC[3:0] Boost/Cut 0000 -12 dB 0001 -12 dB 0010 -10 dB … … 0101 -4 dB 0110 -2 dB 0111 0 dB 1000 +2 dB 1001 +4 dB … … 1100 +10 dB 1101 +12 dB 1110 +12 dB 1111 +12 dB 6.
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Register description 6.6.3 6.6.4 6.6.5 STA559BW Limiter 2 attack/release rate (addr 0x14) D7 D6 D5 D4 D3 D2 D1 D0 L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0 0 1 1 0 1 0 1 0 Limiter 2 attack/release threshold (addr 0x15) D7 D6 D5 D4 D3 D2 D1 D0 L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0 0 1 1 0 1 0 0 1 Description The STA559BW includes two independent limiter blocks.
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STA559BW Register description reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”. In AC mode, the attack and release thresholds are set relative to full-scale.
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Register description Table 66. STA559BW Limiter release rate vs LxR bits LxR[3:0] Release Rate dB/ms 0000 0.5116 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 Fast Slow Anti-clipping mode Table 67.
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STA559BW Register description Table 67. Limiter attack threshold vs LxAT bits (AC mode) (continued) LxAT[3:0] AC (dB relative to fs) 1110 +9 1111 +10 Table 68. Limiter release threshold vs LxRT bits (AC mode) LxRT[3:0] AC (dB relative to fs) 0000 -∞ 0001 -29 0010 -20 0011 -16 0100 -14 0101 -12 0110 -10 0111 -8 1000 -7 1001 -6 1010 -5 1011 -4 1100 -3 1101 -2 1110 -1 1111 0 Dynamic range compression mode Table 69.
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Register description Table 69. STA559BW Limiter attack threshold vs LxAT bits (DRC mode) (continued) LxAT[3:0] DRC (dB relative to Volume) 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 Table 70. Limiter release threshold vs LxRT bits (DRC mode) LxRT[3:0] DRC (db relative to Volume + LxAT) 0000 -∞ 0001 -38 0010 -36 0011 -33 0100 -31 0101 -30 0110 -28 0111 -26 1000 -24 1001 -22 1010 -20 1011 -18 1100 -15 1101 -12 1110 -9 1111 -6 6.
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STA559BW 6.7.2 6.7.3 6.7.4 6.7.
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Register description 6.7.6 6.7.
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STA559BW Register description Reading a set of coefficients from RAM 1. Write 6-bits of address to I2C register 0x16. 2. Write 1 to RA bit in I2C address 0x26. 3. Read top 8-bits of coefficient in I2C address 0x17. 4. Read middle 8-bits of coefficient in I2C address 0x18. 5. Read bottom 8-bits of coefficient in I2C address 0x19. 6. Read top 8-bits of coefficient b2 in I2C address 0x1A. 7. Read middle 8-bits of coefficient b2 in I2C address 0x1B. 8.
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Register description STA559BW Writing a set of coefficients to RAM 1. Write 6-bits of starting address to I2C register 0x16. 2. Write top 8-bits of coefficient b1 in I2C address 0x17. 3. Write middle 8-bits of coefficient b1 in I2C address 0x18. 4. Write bottom 8-bits of coefficient b1 in I2C address 0x19. 5. Write top 8-bits of coefficient b2 in I2C address 0x1A. 6. Write middle 8-bits of coefficient b2 in I2C address 0x1B. 7. Write bottom 8-bits of coefficient b2 in I2C address 0x1C. 8.
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STA559BW Register description Table 71.
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Register description STA559BW Coefficients stored in the user defined coefficient RAM are referenced in the following manner: CxHy0 = b1 / 2 CxHy1 = b2 CxHy2 = -a1 / 2 CxHy3 = -a2 CxHy4 = b0 / 2 where x represents the channel and the y the biquad number. For example, C2H41 is the b2 coefficient in the fourth biquad for channel 2.
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STA559BW 6.8 Register description Variable max power correction registers (addr 0x27 - 0x28) D7 D6 D5 D4 D3 D2 D1 D0 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0 0 0 1 1 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 1 1 0 0 0 0 0 0 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 6.
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Register description 6.11 STA559BW Device status register (addr 0x2D) D7 D6 D5 D4 D3 D2 D1 D0 PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.
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STA559BW Applications 7 Applications 7.1 Applications schematic Figure 19 below shows the typical applications schematic for STA559BW. Special attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be placed as close as possible to the device to limit spikes on all the supplies. 7.2 PLL filter circuit It is recommended to use the above circuit and values for the PLL loop filter to achieve the best performance from the device in general applications.
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Applications 62/67 Figure 19.
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STA559BW 8 Package thermal characteristics Package thermal characteristics Using a double-layer PCB the thermal resistance, junction to ambient, with 2 copper ground areas of 3 x 3 cm2 and with 16 via holes is 24 °C/W in natural air convection. The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level.
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Package mechanical data 9 STA559BW Package mechanical data Figure 21 shows the package outline and Table 72 gives the dimensions. Table 72. PowerSSO-36 EPD dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.00 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.
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h x 45° STA559BW Figure 21.
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Revision history 10 STA559BW Revision history Table 73. 66/67 Document revision history Date Revision 17-Dec-2010 1 Changes Initial release.
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STA559BW Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.