Datasheet

Practical information STA540
22/25 Doc ID 13907 Rev 6
6.9 PCB ground layout
The device has two distinct ground pins, P-GND (power ground) and S-GND (signal ground)
which are disconnected from each other at chip level. For superior performance the pins
P-GND and S-GND must be connected together on the PCB by low-resistance tracks.
For the PCB-ground configuration, a star-like arrangement, where the center is represented
by the supply-filtering electrolytic capacitor ground, is recommended. In an arrangement
such as this, at least two separate paths must be provided, one for P-GND and one for
S-GND.
The correct ground assignments are as follows:
● on S-GND:
– standby capacitor (pin 7, or any other standby driving networks),
– SVR capacitor (pin 6), to be placed as close as possible to the device,
– input signal ground (from active/passive signal processor stages)
● on P-GND:
– power supply filtering capacitors for pins 3 and 13. The negative terminal of the
electrolytic capacitor(s) must be directly tied to the battery negative line and this
should represent the starting point for all the ground paths.
6.10 Mute function
If the mute function is desired, it can be implemented on pin 6, SVR, as shown in Figure 29.
Figure 29. Optional mute function circuit
Using a different value for R1 than the suggested 3.3 kΩ, results in two different situations:
● R1 > 3.3 kΩ:
– pop noise improvement,
– lower mute attenuation;
● R1 < 3.3 kΩ:
– pop noise degradation,
– higher mute attenuation.
0.22μF
1
DIAGNOSTICS
4
7
D06AU1632
10μF
10K
ST-BY
IN L
0.47μF
5
IN BRIDGE 12
470μF
6
13
1000μF100nF
3
V
S
2
15
14
OUT L
8
9
10
OUT
BRIDGE
11
0.22μF
IN R
OUT R
2200μF
2200μF
R1 3.3K
R2 10K
MUTE
5V
0
PLAY
V
S
= 10 to 16 V,
mute off: V
SVR
≥ 0.6 to 0.8 V,
mute on: V
SVR
≥ 0.2 V