Datasheet

Introduction STA516B
2/18 DocID13183 Rev 5
1 Introduction
Figure 1. Application circuit (dual BTL)
L18 22 H
L19 22 H
C3 0
1F
C2 0
100nF
C9 9
100nF
C101
100nF
C107
100nF
C106
100nF
C2 3
470nF
C5 5
1000
F
C2 1
100nF
C5 8
100nF
C5 8
100nF
R5 7
10K
R5 9
10K
R6 3
20
R9 8
6
R100
6
C5 3
100nF
C6 0
100nF
C3 1
1F
C5 2
330pF
R104
20
C109
330pF
15
M3
IN1A
IN1A
V
L
CON FI G
PWRDNPWRDN
FAULT
TRI-STATE
TH_WA R
T
H_WAR
+3.3V
IN1B
V
DD
V
DD
V
SS
V
SS
V
CC
SI G N
V
CC
SI G N
GND- Reg
GND- Cl ea n
IN2A
IN1B
IN2A
IN2B
PROTECTIONS
&
LOGIC
REG U L A T O RS
29
23
24
25
27
26
28
30
21
22
33
34
35
36
M2
M5
M4
17
16
OUT1A
GND1 A
OUT1A
V
CC
1A
14
12
10
11
OUT1B
GND1 B
OUT1B
V
CC
1B
13
L113 22 H
L112 22 H
C3 2
1F
+V
CC
C108
470nF
C3 3
1F
7
M17
M15
M16
M14
8
9
OUT2A
GND2 A
OUT2A
V
CC
2A
6
4
2
3
OUT2B
GND2 B
D00AU1148
B
OUT2B
V
CC
2B
5
19
31
20
GNDSUB
1
IN2B 32
C110
100nF
C111
100nF
R103
6
R102
6
8
8