Datasheet

Applications information STA333W
40/49 Doc ID 13365 Rev 2
Figure 12. PLL filter circuit
7.3 Typical output configuration
Figure 13 below shows a typical output configuration used for BTL stereo mode.
Figure 13. Output configuration for stereo BTL mode
100pF
FILTER_PLL
680pF
4.7nF
2K2
100pF
FILTER_PLL
680pF
4.7nF
2K2
BEAD
PLL_GNDGND_DIG
100pF
FILTER_PLL
680pF
4.7nF
2K2
100pF
FILTER_PLL
680pF
4.7nF
2K2
BEADBEAD
PLL_GNDGND_DIG
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
LEFT
100nF
6.2
OUT1A
OUT1B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
RIGHT
100nF
6.2
OUT2A
OUT2B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
LEFT
100nF
6.2
OUT1A
OUT1B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
LEFT
100nF
6.2
OUT1A
OUT1B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
RIGHT
100nF
6.2
OUT2A
OUT2B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
RIGHT
100nF
6.2
OUT2A
OUT2B
6.2