Datasheet

STA333W Applications information
Doc ID 13365 Rev 2 39/49
7 Applications information
7.1 Applications scheme for power supplies
Figure 11 below shows a typical applications scheme for STA333W.
Special care has to be taken with regard to the power supplies when laying out the PCB. In
particular the 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close
as possible to the device. This prevents unwanted oscillation on the digital parts of the
device due to the inductive effects of the PCB tracks. The same rule also applies to all the
decoulpling capacitors; they should be placed as close as possible to the device in order to
limit the effect of spikes on the supplies.
Figure 11. Applications diagram
7.2 PLL filter
It is recommended to use the circuit in Figure 12 below for the PLL loop filter to achieve the
best performance from the device in general applications. Note that the ground of this filter
has to be connected to the ground of the PLL without any resistive path.
For the component values, it should be remembered that the greater the filter bandwidth, the
shorter the lock time but the higher the PLL output jitter.
9
8
100nF
+
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
3V3
1uF 35V
100nF
100nF
1uF 35V
INTL
100nF
100nF
3V3
3V3
3R3
3R3
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
OUT2A
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
NC
17
NC
18
NC
19
NC
20
VDD_DIG
21
GND_DIG
22
PWRDN
23
VDD_PLL
24
FILTER_PLL
25
PLL_GND
26
XTI
27
BICKI
28
LRCKI
29
SDI
30
RESET
31
INT_LINE
32
SDA
33
SCL
34
GND_DIG
35
VDD_DIG
36
OUT1B
DATA
PLL_FILT
OUT1A
10K
100nF
1nF
SCL
SDA
RESET
RESET
100nF
100nF
OUT2A
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
DATA
PLL_FILT
BEAD
BEADBEAD
PLL_GND
GND_DIG
GND_DIG
GND_DIG
GND_DIG
9
8
100nF
+
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
3V3
1uF 35V
100nF
100nF
1uF 35V
INTL
100nF
100nF
3V3
3V3
3R3
3R3
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
OUT2A
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
NC
17
NC
18
NC
19
NC
20
VDD_DIG
21
GND_DIG
22
PWRDN
23
VDD_PLL
24
FILTER_PLL
25
PLL_GND
26
XTI
27
BICKI
28
LRCKI
29
SDI
30
RESET
31
INT_LINE
32
SDA
33
SCL
34
GND_DIG
35
VDD_DIG
36
OUT1B
DATA
PLL_FILT
OUT1A
10K
100nF
1nF
SCL
SDA
RESET
RESET
100nF
100nF
OUT2A
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
DATA
PLL_FILT
BEAD
BEADBEAD
PLL_GND
GND_DIG
GND_DIG
GND_DIG
GND_DIG
9
8
100nF
+
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
3V3
1uF 35V
100nF
100nF
1uF 35V
INTL
100nF
100nF
3V3
3V3
3R3
3R3
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
OUT2A
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
NC
17
NC
18
NC
19
NC
20
VDD_DIG
21
GND_DIG
22
PWRDN
23
VDD_PLL
24
FILTER_PLL
25
PLL_GND
26
XTI
27
BICKI
28
LRCKI
29
SDI
30
RESET
31
INT_LINE
32
SDA
33
SCL
34
GND_DIG
35
VDD_DIG
36
OUT1B
DATA
PLL_FILT
OUT1A
10K
100nF
1nF
SCL
SDA
RESET
RESET
100nF
100nF
OUT2A
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
DATA
PLL_FILT
BEAD
BEADBEAD
PLL_GND
GND_DIG
GND_DIG
GND_DIG
GND_DIG