Datasheet

Register description STA333W
36/49 Doc ID 13365 Rev 2
6.6 Variable distortion compensation registers (addr 0x29, 0x2A)
DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient
is used in place of the default coefficient when DCCV = 1.
6.7 Fault detect recovery constant registers (addr 0x2B, 0x2C)
FDRC bits specify the 16-bit fault detect recovery time delay. When status register bit FAULT
is asserted, the tristate output is immediately asserted low and held low for the time period
specified by this constant. A value of 0x0001 in this register is approximately 0.083 ms. The
default value of 0x000C gives approximately 0.1 ms.
Note: 0x0000 is a reserved value for this register pair. This value must not be used.
6.8 Device status register (addr 0x2D)
This read-only register provides the fault, warning and PLL status from the power control
block.
D7 D6 D5 D4 D3 D2 D1 D0
DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8
11110011
D7 D6 D5 D4 D3 D2 D1 D0
DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0
00110011
D7 D6 D5 D4 D3 D2 D1 D0
FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8
00000000
D7 D6 D5 D4 D3 D2 D1 D0
FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0
00001100
D7 D6 D5 D4 D3 D2 D1 D0
PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN
Table 45. Status bits description
Bit R/W RST Name Description
0RO- TWARN
Thermal warning:
0: junction temperature is close to the fault condition
1: normal operation
1RO- TFAULT
Thermal fault:
0: junction temperature limit detection
1: normal operation