Datasheet

STA333W Register description
Doc ID 13365 Rev 2 35/49
6.4 Channel configuration registers (addr 0x0E, 0x0F)
Volume bypass
Each channel contains an individual channel volume bypass. If a particular channel has
volume bypassed via the CxVBP = 1 register then only the channel volume setting for that
particular channel affects the volume setting, the master volume setting will not affect that
channel.
6.5 Variable max power correction registers (addr 0x27, 0x28)
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is
used in place of the default coefficient when MPCV = 1.
010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz
011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz
100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz
101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz
110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz
Table 44. Automodes™ AM switching frequency selection
D7 D6 D5 D4 D3 D2 D1 D0
Reserved C1VBP Reserved
00000000
D7 D6 D5 D4 D3 D2 D1 D0
Reserved C2VBP Reserved
00000000
D7 D6 D5 D4 D3 D2 D1 D0
MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8
00011010
D7 D6 D5 D4 D3 D2 D1 D0
MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0
11000000