Datasheet

32/49 Doc ID 13365 Rev 2

6.2 Volume control registers (addr 0x06 to 0x09)

6.2.1 Mute/line output configuration register (addr 0x06)

Master mute

Channel mute

D7 D6 D5 D4 D3 D2 D1 D0

Reserved C2M C1M MMUTE

00000000

Table 39. Master mute

Bit R/W RST Name Description

0R/W0MMUTE

0: normal operation

1: all channels are in mute condition

Table 40. Channel mute

Bit R/W RST Name Description

1R/W0C1M

Channel 1 mute:

0: not muted, it is possible to set the channel volume

1: hardware muted

2R/W0C2M

Channel 2 mute:

0: not muted, it is possible to set the channel volume

1: hardware muted