Datasheet

STA333W Register description
Doc ID 13365 Rev 2 31/49
LRCK double trigger protection
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
When active will issue a power device power-down signal (EAPD) on clock loss detection.
IC power down
The PWDN register is used to put the IC in a low-power state. When PWDN is 0, the output
begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down
the power stage, then the master clock to all internal hardware except the I
2
C block is gated.
This puts the IC in a very low power consumption state.
External amplifier power down
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled).
Table 35. LRCK double trigger protection
Bit R/W RST Name Description
4 R/W 1 LDTE LRCLK double trigger protection enable
Table 36. Auto EAPD on clock loss
Bit R/W RST Name Description
5 R/W 0 ECLE Auto EAPD on clock loss
Table 37. Power down
Bit R/W RST Name Description
6R/W1PWDN
0: power down, low-power condition
1: normal operation
Table 38. External amplifier power down
Bit R/W RST Name Description
7 R/W 1 EAPD
0: external power stage power down active
1: normal operation