Datasheet

STA333W Register description
Doc ID 13365 Rev 2 27/49
Channel input mapping
Each channel received via I
2
S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I
2
S input channel to its corresponding processing channel.
6.1.3 Configuration register C (addr 0x02)
DDX power output mode
DDX compensation pulse size register
Table 20. Channel input mapping
Bit R/W RST Name Description
6R/W0C1IM
0: processing channel 1 receives left I
2
S input
1: processing channel 1 receives right I
2
S input
7R/W0C2IM
0: processing channel 2 receives left I
2
S input
1: processing channel 2 receives right I
2
S input
D7 D6 D5 D4 D3 D2 D1 D0
OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0
10010111
Table 21. DDX power output mode
Bit R/W RST Name Description
0 R/W 1 OM0 The DDX power output mode selects the configuration
of the DDX output:
00: drop compensation
01: discrete output stage: tapered compensation
10: full-power mode
11: variable drop compensation (CSZx bits)
1R/W1OM1
Table 22. DDX compensating pulse size
Bit R/W RST Name Description
2 R/W 1 CSZ0 When OM[1:0] = 11, this register determines the size of
the DDX compensating pulse from 0 to 15 clock periods:
0000: 0 ns (0 ticks) compensating pulse size
0001: 20 ns (1 tick) clock period compensating pulse
size
.....
1111: 300 ns (15 ticks) clock period compensating pulse
size
3R/W0CSZ1
4R/W1CSZ2
5R/W0CSZ3