Datasheet

Register description STA333W
22/49 Doc ID 13365 Rev 2
6.1 Configuration registers (addr 0x00 to 0x05)
6.1.1 Configuration register A (addr 0x00)
Master clock select
The STA333W supports sample rates of 32 kHz, 44.1 kHz, 48 KHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
z 32.768 MHz for 32 kHz
z 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
z 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (f
S
).
The relationship between the input clock and the input sample rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally.
D7 D6 D5 D4 D3 D2 D1 D0
FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0
01100011
Table 9. Master clock select
Bit R/W RST Name Description
0R/W1MCS0
Master clock select: Selects the ratio between the
input I
2
S sample frequency and the input clock.
1R/W1MCS1
2R/W0MCS2
Table 10. MCS bits
Input sample rate
f
S
(kHz)
IR
MCS[2:0]
101 100 011 010 001 000
32, 44.1, 48 00 576 * f
S
128 * f
S
256 * f
S
384 * f
S
512 * f
S
768 * f
S
88.2, 96 01 NA 64 * f
S
128 * f
S
192 * f
S
256 * f
S
384 * f
S
176.4, 192 1X NA 32 * f
S
64 * f
S
96 * f
S
128 * f
S
192 * f
S