Datasheet

Functional description STA333W
16/49 Doc ID 13365 Rev 2
4 Functional description
4.1 Functional pins
4.1.1 Power-down function
Pin PWRDN (23) is used to power down the STA333W.
PWRDN = 0 (0 V): power-down state.
PWRND = 1 (V
DD
): normal operation.
During the power-down sequence the output begins to mute. After the mute condition is
reached the power stage is switched off and the output becomes high impedance. Then the
master clock to all internal hardware blocks is gated off. The PLL is also switched off. The
complete power-down sequence takes 13 million cycles.
4.1.2 Reset function
Pin RESET (31) is used to reset the STA333W.
RESET = 0 (0 V): reset state.
RESET = 1 (V
DD
): normal operation.
When pin RESET is forced to 0 the power stage is switched off (with high-impedance
output) and the master clock to all internal hardware blocks is gated off.
Note: Reset has a higher priority than power down.