Datasheet

Electrical specification STA333W
14/49 Doc ID 13365 Rev 2
3.5 Power-on/off sequences
The power-on/off sequences shown in Figure 3 and Figure 4 below ensure a pop-free turn
on and turn off.
Figure 3. Power-on sequence
Figure 4. Power-off sequence
Don’t care
VCC
VDD_Dig
XTI
Reset
TR
Don’t care
Don’t care
PWRDN
Soft EAPD
Reg. 0x05
Bit 7 = 1
TC
Don’t care
VCC
VDD_Dig
XTI
Reset
TR
Don’t care
Don’t care
PWRDN
Soft EAPD
Reg. 0x05
Bit 7 = 1
TC
TR = mimimum time between XTI master clock stable and reset removal: 1 ms
TC = minimum time between reset removal and I
2
C program sequence start: 1 ms
No specific VCC and VDD_DIG turn-on sequence is required
Clock stable means: fmax - fmin < 1 MHz
VCC
VDD_DIG
XTI
RESET
PWRDN
Bit EAPD
Register 0x05
Don’t care
VCC
VDD_Dig
XTI
Don’t care
Soft Mute
Reg. 0x07
Data 0xFE
Soft EAPD
Reg. 0x05
Bit 7 = 0
Don’t care
FE
Don’t care
Don’t care
Don’t care
VCC
VDD_Dig
XTI
Don’t care
Soft Mute
Reg. 0x07
Data 0xFE
Soft EAPD
Reg. 0x05
Bit 7 = 0
Don’t care
FE
Don’t care
Don’t care
No specific VCC and VDD_DIG turn-off sequence is required
VCC
VDD_DIG
XTI
Mute
Bit EAPD
Register 0x05
Register 0x07