Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsLinear ICsLinear IC - Custom audio Pre-amp I²C, I²S PowerSSO 36

January 2010 Doc ID 13365 Rev 2 1/49

STA333W

2-channel high-efficiency digital audio system

Sound Terminal™

Features

 Wide supply-voltage range (4.5 V - 20 V)

 2 power output configurations

– 2 channels of binary PWM (stereo mode)

– 2 channels of ternary PWM (stereo mode)

 PowerSSO-36 with exposed pad down

 2 channels of 24-bit DDX



100-dB SNR and dynamic range

 Selectable 32- to 192-kHz input sample rates

 I

C control with selectable device address

 Digital gain -80 dB to +48 dB in 0.5-dB steps

 Software volume update

 Individual channel and master gain/attenuation

 Individual channel and master software and

hardware mute

 Independent channel volume bypass

 Automatic zero-detect mute

 Automatic invalid input detect mute

 2-channel I

S input data Interface

 Selectable clock input ratio

 Input channel mapping

 Automatic volume control for limiting maximum

power

 96-kHz internal processing sample rate, 24-bit

precision

 Advanced AM interference frequency

switching and noise suppression modes

 Thermal-overload and short-circuit protection

embedded

 Video application: 576 * f

input mode support

Applications

 LCD

 DVD

 Cradle

 Digital speaker

 Wireless-speaker cradle

Description

The STA333W is an integrated circuit comprising

digital audio processing, digital amplifier control

and DDX

power output stage to create a high-

power, single-chip DDX

solution for all-digital

amplification with high quality and high efficiency.

The STA333W power section consists of four

independent half-bridges stages. These can be

configured via digital control to operate in different

modes. 2 channels can be provided by two full

bridges, providing up to 20 W + 20 W of power.

Also provided in the STA333W are new advanced

AM radio interference reduction modes. The serial

audio data input interface accepts all possible

formats, including the popular I

S format. Three

channels of DDX

processing are provided.

The STA333W is part of the Sound Terminal™

family that provides full digital audio streaming to

the speaker offering cost effectiveness, low power

dissipation and sound enrichment.

PowerSSO-36 package

with exposed

pad down (EPD)

Table 1. Device summary

Order code Package Packaging

STA333W PowerSSO-36 EPD Tube

STA333W13TR PowerSSO-36 EPD Tape and reel

www.st.com

Summary of content (49 pages)

PAGE 1
STA333W 2-channel high-efficiency digital audio system Sound Terminal™ Features Wide supply-voltage range (4.5 V - 20 V) 2 power output configurations – 2 channels of binary PWM (stereo mode) – 2 channels of ternary PWM (stereo mode) PowerSSO-36 with exposed pad down 2 channels of 24-bit DDX® 100-dB SNR and dynamic range Selectable 32- to 192-kHz input sample rates I2C control with selectable device address Digital gain -80 dB to +48 dB in 0.
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Contents STA333W Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 2.1 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.
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STA333W 6 Contents 5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents STA333W 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 47 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STA333W List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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List of figures STA333W List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. 6/49 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connection (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . .
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STA333W 1 Block diagram Block diagram Figure 1.
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Pin description STA333W 2 Pin description 2.1 Pin out Figure 2. Pin connection (package top view) GND_SUB 1 36 VDD_DIG SA 2 35 GND_DIG TEST_MODE 3 34 SCL VSS 4 33 SDA VCC_REG 5 32 INT_LINE OUT2B 6 31 RESET GND2 7 30 SDI VCC2 8 29 LRCKI OUT2A 9 28 BICKI OUT1B 10 27 XTI VCC1 11 26 GND_PLL GND1 12 25 FILTER_PLL VDD_PLL OUT1A 13 GND_REG 14 VDD_REG 15 24 EP exposed pad (down) 23 Connect to ground 22 CONFIG 16 21 VDD_DIG N.C. 17 20 N.C. N.C.
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STA333W Pin description Table 2. Pin description (continued) Number Type Name Description 10 O OUT1B Output half bridge 1B 11 PWR VCC1 Power positive supply 12 PWR GND1 Power negative supply 13 O OUT1A Output half bridge 1A 14 PWR GND_REG Internal ground reference 15 PWR VDD_REG Internal 3.3-V reference voltage 16 I CONFIG Paralleled mode command 17 - N.C. No internal connection 18 - N.C. No internal connection 19 - N.C. No internal connection 20 - N.C.
PAGE 10
Pin description 2.3 STA333W Thermal data Table 3. Symbol Thermal data Parameter RTh(j-case) Thermal resistance junction to case (thermal pad) 10/49 Min Typ Max Unit - 1.5 2.
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STA333W Electrical specification 3 Electrical specification 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Parameter Typ Max Unit VCC Analog supply voltage (pins VCCx) - - 23 V VDD Digital supply voltage (pins VDD_DIG) - - 4.0 V IL Logic input interface -0.3 - 4.0 V Top Operating junction temperature 0 - 150 °C Tstg Storage temperature -40 - 150 °C Warning: 3.
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Electrical specification 3.3 STA333W Electrical specifications - digital section Table 6. Electrical characteristics for digital section Symbol Iil Conditions Min Typ Max Unit Input current, no pull-up or pull-down resistor Vi = 0 V - - ±10 µA Vi = VDD = 3.6 V - - ±10 µA Vil Low-level input voltage - - - 0.2 * VDD V Vih High-level input voltage - 0.8 * VDD - - V Vol Low-level output voltage Iol = 2 mA - - 0.4 * VDD V Voh High-level output voltage Ioh = 2 mA 0.
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STA333W Electrical specification Table 7. Symbol VCC IVCC IVDD_DIG Electrical specifications for power section (continued) Parameter Conditions Min Typ Max Unit Supply voltage - 4.5 - 20 V Supply current from VCC in power down PWRDN = 0 30 60 200 µA Supply current from VCC in operation PCM input signal = -60 dBfs Switching frequency = 384 kHz No LC filters - 30 50 mA Supply current for DDX Internal clock = 49.
PAGE 14
Electrical specification 3.5 STA333W Power-on/off sequences The power-on/off sequences shown in Figure 3 and Figure 4 below ensure a pop-free turn on and turn off. Figure 3. Power-on sequence No specific VCC and VDD_DIG turn-on sequence is required VCC VCC Don’t care VDD_Dig VDD_DIG XTI XTI Don’t care Reset RESET TR PWRDN PWRDN Bit EAPD Soft EAPD Register Reg.
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STA333W 3.6 Electrical specification Testing Figure 5. Test circuit OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - V67 = vdc = Vcc/2 gnd Figure 6.
PAGE 16
Functional description STA333W 4 Functional description 4.1 Functional pins 4.1.1 Power-down function Pin PWRDN (23) is used to power down the STA333W. PWRDN = 0 (0 V): power-down state. PWRND = 1 (VDD): normal operation. During the power-down sequence the output begins to mute. After the mute condition is reached the power stage is switched off and the output becomes high impedance. Then the master clock to all internal hardware blocks is gated off. The PLL is also switched off.
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STA333W Functional description 4.2 Serial audio interface description 4.2.1 Serial audio interface protocols The STA333W serial audio input was designed to interface with standard digital audio components and to accept serial data formats. The STA333W always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28), and serial data SDI (pin 30).
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I2C bus specification 5 STA333W I2C bus specification The STA333W supports the I2C protocol via the input ports SCL and SDA. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA333W is always a slave device in all of its communications.
PAGE 19
I2C bus specification STA333W 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA333W acknowledges this and then waits for the byte of internal address. After receiving the internal byte address the STA333W again responds with an acknowledgement. 5.3.1 Byte write In the byte write mode the master sends one data byte, this is acknowledged by the STA333W. The master then terminates the transfer by generating a STOP condition. 5.3.
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I2C bus specification 5.4.4 STA333W Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333W. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer. Figure 10.
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STA333W 6 Register description Register description Table 8.
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Register description STA333W 6.1 Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00) D7 D6 D5 D4 D3 D2 D1 D0 FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0 0 1 1 0 0 0 1 1 Master clock select Table 9. Master clock select Bit R/W RST Name 0 R/W 1 MCS0 1 R/W 1 MCS1 2 R/W 0 MCS2 Description Master clock select: Selects the ratio between the input I2S sample frequency and the input clock. The STA333W supports sample rates of 32 kHz, 44.
PAGE 23
STA333W Register description Interpolation ratio select Table 11. Bit 4:3 Interpolation ratio select R/W R/W RST 00 Name IR [1:0] Description Interpolation ratio select: Selects internal interpolation ratio based on input I2S sample frequency. The STA333W has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2-times downsample.
PAGE 24
Register description STA333W Thermal warning adjustment bypass Table 14. Bit 6 Thermal warning adjustment R/W RST R/W 1 Name Description Thermal warning adjustment bypass: 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled TWAB The on-chip STA333W power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition.
PAGE 25
STA333W Register description Serial audio input interface format Table 16. Bit Serial audio input interface format R/W RST Name 0 R/W 0 SAI0 1 R/W 0 SAI1 2 R/W 0 SAI2 3 R/W 0 SAI3 Description Determines the interface format of the input serial digital audio interface. Serial data interface The STA333W audio serial input interfaces with standard digital audio components and accepts a number of serial data formats.
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Register description Table 18. STA333W Support serial audio input formats for MSB first (SAIFB = 0) (continued) 64* fS Table 19.
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STA333W Register description Channel input mapping Table 20. Bit Channel input mapping R/W RST Name Description 6 R/W 0 C1IM 0: processing channel 1 receives left I2S input 1: processing channel 1 receives right I2S input 7 R/W 0 C2IM 0: processing channel 2 receives left I2S input 1: processing channel 2 receives right I2S input Each channel received via I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing.
PAGE 28
Register description STA333W Overcurrent warning detect adjustment bypass Table 23. Bit 7 Overcurrent warning detect adjustment bypass R/W RST R/W 1 Name Description 0: overcurrent warning adjustment enabled 1: overcurrent warning adjustment disabled OCRB The status bit OCWARN is used to warn of an overcurrent condition.
PAGE 29
STA333W Register description Max power correction Table 26. Bit 1 Max power correction R/W R/W RST 1 Name MPC Description 1: enable power bridge correction for THD reduction near maximum power output. Setting the MPC bit turns on special processing that corrects the STA333W power device at high power. This mode lowers the THD+N of a full DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1:0] = 01) and binary.
PAGE 30
Register description STA333W Zero-crossing volume enable Table 31. Bit 6 Zero-crossing volume enable R/W RST R/W 1 Name Description 1: volume adjustments will only occur at digital zero-crossings 0: volume adjustments will occur immediately ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. Soft volume update enable Table 32. Bit 7 6.1.
PAGE 31
STA333W Register description LRCK double trigger protection Table 35. Bit 4 LRCK double trigger protection R/W R/W RST 1 Name Description LDTE LRCLK double trigger protection enable Actively prevents double trigger of LRCLK. Auto EAPD on clock loss Table 36. Bit 5 Auto EAPD on clock loss R/W R/W RST 0 Name ECLE Description Auto EAPD on clock loss When active will issue a power device power-down signal (EAPD) on clock loss detection. IC power down Table 37.
PAGE 32
Register description STA333W 6.2 Volume control registers (addr 0x06 to 0x09) 6.2.1 Mute/line output configuration register (addr 0x06) D7 D6 D5 D4 D3 Reserved 0 0 0 0 0 D2 D1 D0 C2M C1M MMUTE 0 0 0 Master mute Table 39. Bit 0 Master mute R/W R/W RST 0 Name MMUTE Description 0: normal operation 1: all channels are in mute condition Channel mute Table 40.
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STA333W 6.2.2 6.2.
PAGE 34
Register description STA333W Table 42. Channel volume as a function of CxV CxV[7:0] 6.3 Volume 00000000 (0x00) +48 dB 00000001 (0x01) +47.5 dB 00000010 (0x02) +47 dB … … 01011111 (0x5F) +0.5 dB 01100000 (0x60) 0 dB 01100001 (0x61) -0.5 dB … … 11010111 (0xD7) -59.
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STA333W Register description Table 44. 6.4 Automodes™ AM switching frequency selection 010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz 011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz 100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz 101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz 110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.
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Register description 6.6 STA333W Variable distortion compensation registers (addr 0x29, 0x2A) D7 D6 D5 D4 D3 D2 D1 D0 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 1 1 1 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0 0 1 1 0 0 1 1 DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. 6.
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STA333W Register description Table 45. Bit 6.
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Register description STA333W 6.11 Output limit register (addr 0x34) 6.11.1 Thermal and overcurrent warning output limit register D7 D6 D5 D4 D3 D2 D1 D0 OLIM7 OLIM6 OLIM5 OLIM4 OLIM3 OLIM2 OLIM1 OLIM0 0 1 0 1 1 0 1 0 The STA333W provides a simple mechanism for reacting to a thermal or overcurrent warning in the power device. When the TWARN or OCWARN status bit is asserted, the output is limited to the OLIM setting.
PAGE 39
STA333W Applications information 7 Applications information 7.1 Applications scheme for power supplies Figure 11 below shows a typical applications scheme for STA333W. Special care has to be taken with regard to the power supplies when laying out the PCB. In particular the 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This prevents unwanted oscillation on the digital parts of the device due to the inductive effects of the PCB tracks.
PAGE 40
Applications information STA333W Figure 12. PLL filter circuit F IL T E R _ P L L 2K2 680pF 100pF 4 .7 n F BEAD G N D _ D IG 7.3 PLL_G ND Typical output configuration Figure 13 below shows a typical output configuration used for BTL stereo mode. Figure 13. Output configuration for stereo BTL mode 22uH OUT1A 100nF 6.2 22 6.2 330pF 100nF 470nF LEFT 470nF RIGHT 100nF 100nF OUT1B 22uH 22uH OUT2A 100nF 6.2 22 6.
PAGE 41
STA333W Characterization data The following characterizations were made with RL = 8 Ω and f = 1 kHz unless otherwise stated. Figure 14. Output power vs. supply voltage (THD = 1%) 30 RKP 25 Output power, W 8 Characterization data 20 6 Ω RKP 4Ω 15 8 Ω RKP 10 16 Ω RKP 5 0 5 7 9 11 13 15 17 19 Supply voltage, V Figure 15.
PAGE 42
Characterization data STA333W Figure 16. FFT -60 dBfs (VCC = 12 V) +10 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 17. THD vs. frequency (VCC = 12 V, Po = 1 W) 1 0.5 6ohm 6 0.2 % 4ohm 4Ω Ω 0.1 0.05 8Ω 8ohm 0.02 0.
PAGE 43
STA333W Characterization data Figure 18. FFT 0 dBfs (VCC = 18 V) +10 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k 1k 2k 5k 10k 20k 10k 20k Hz Figure 19. FFT -60 dBfs (VCC = 18 V) +10 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 Hz Figure 20. THD vs. frequency (VCC = 18 V, Po = 1 W) 1 0.5 6ohm 6Ω 4ohm 4 Ω 0.2 0.1 % 0.05 8ohm 8 0.02 Ω 0.
PAGE 44
Package thermal characteristics 9 STA333W Package thermal characteristics A thermal resistance of 25 °C/W can be achieved by mounting the device on a PCB which has two copper ground areas of 3 x 3 cm and 16 vias (see Figure 21). Given that the amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level the maximum estimated dissipated power for the STA333W is 3 W.
PAGE 45
STA333W Package mechanical data The STA333W comes in a 36-pin PowerSSO package with exposed pad down (EPD). Figure 23 below shows the package outline and Table 47 gives the dimensions. Figure 23.
PAGE 46
Package mechanical data Table 47. STA333W PowerSSO-36 EPD dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.000 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.
PAGE 47
STA333W 11 Trademarks and other acknowledgements Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. Automodes is a trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. Sound Terminal is a trademark of STMicroelectronics.
PAGE 48
Revision history 12 STA333W Revision history Table 48. Document revision history Date Revision 25-May-2007 1 Initial release. 2 Updated features for operating voltage range, digital gain increments and maximum power control on page 1 Updated description on page 1 Updated electrical specifications Table 4, Table 3 and Table 5 on page 11 Added Section 3.
PAGE 49
STA333W Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.