Datasheet

STA333ML Electrical specifications
Doc ID 13177 Rev 6 9/21
3.6 Power-on sequence
Figure 3. Power-on sequence
3.7 Test circuits
Figure 4. Resistive load
Figure 5. Test circuit
Don’t care
VCC
VDD_Dig
XTI
Reset
PWDN
TR
Don’t care
VCC
VDD_Dig
XTI
Reset
PWDN
TR
Don’t care
Don’t care
VCC
VDD_Dig
XTI
Reset
PWDN
TR
Don’t care
VCC
VDD_Dig
XTI
Reset
PWDN
TR
Don’t care
TR = minimum time between XTI master clock stable and reset removal: 1 ms
Note 1: clock stable means: f
max
- f
min
< 1 MHz
Note 2: No specific V
CC
and V
DD
turn-on sequence is required.
Low current dead time = MAX(DTr,DTf)
OUTxY
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
t
DTfDTr
Duty cycle = 50%
INxY
OUTxY
gnd
+Vcc
M58
M57
R 8Ω
+
-
V67 =
vdc = Vcc/2
D03AU1458
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Rload=8Ω
Q2
OUTB
)B(niTD)B(tuoTD
DTout(A)
C71 470nF
C70
470nF
C69
470nF
Iout=4AIout=4A
Q4
Q1
Q3
M64
INB
M63
D03AU1517
M58
INA
M57
DTin(A)
Duty cycle=A
Duty cycle=B
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
L68 22µL67 22µ
OUTA
Lout = 1.5 A
Lout = 1.5 A