Datasheet

Applications STA333ML
14/21 Doc ID 13177 Rev 6
5.2 Internal voltage reference
An embedded voltage regulator produces the reference voltages for the DMOS bridge
driver. It requires two 100 nF capacitors to keep the regulator stable. The capacitors should
be place close to the pins.
Figure 9. Reference voltage block diagram
5.3 PLL filter schematic
It is recommended to use the below scheme and values for the PLL loop filter to achieve the
best performances from the device in general application. Please note that the ground of
this filter scheme has to be connected to the ground of the PLL without any resistive path.
Concerning the component values, please take into account that the greater the filter
bandwidth, the less the lock time, but the higher the PLL output jitter.
Figure 10. PLL application schematic
VCC_REG
VSS_REG
VDD_REG
GND_REG
100 nF
100 nF
Regulator
Input
I
2
S
Driver P
Driver N
level
shifter
interface
GND
VCC
4.7n
2.2K
680p
0
PLL_FILTER