Datasheet

STA309A Block diagram
Doc ID 13855 Rev 4 9/67
1 Block diagram
Figure 1. Block diagram
Figure 2. Channel signal flow
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
OUT6A/B
OUT7A/B
OUT8A/B
LRCKI
BICKI
SDI12
SDI34
SDI56
SDI78
SA
SERIAL
DATA
IN
I
2
C
CHANNEL
MAPPING
VARIABLE
OVER-
SAMPLING
TREBLE,
BASS, EQ
(
BIQUADS
)
VOLUME
LIMITING
SDO78
SDO12
SDO34
SDO56
OVERSAMPLING
VARIABLE
DOWN-
SAMPLING
POWER
DOWN
PWDN
EAPD
PLL
PLLB
XTI
CKOUT
SCL
SDA
LRCKO
BICKO
MVO
SERIAL
DATA
OUT
SYSTEM
CONTROL
SYSTEM TIMING
DDX
1x,2x,4x
Interp
Biq uads
B/T
Volume
Limiter
2x
Interp
Distortion
Compensation
NS C_Con PWM
DDX
Output
Interp_Rate
8 Inputs
From I2S
DSD
Conversion
6 Inputs
From DSD
Mapping/
Mix #1
DSDE
Mix #2
PreScale
Hig h- P as s
Filter
Biq u ad
#2
Biquad
#3
Biquad
#4
Biq u a d
#5
Biquad
#6
Biquad
#7
Biquad
#8
Ba ss
Hard Set to
-18dB when
AutoMode EQ
(AMEQ)
Hard Set Coeffecients when AutoMode EQ
(AMEQ)
Hard S et
Coeffec ients w hen
Au to Mo de
Bass Management
Cross over
(AMBMXE)
Har d Se t
Coeffec ients when
DeEmphasis
Enabled
(DEMP)
From
Mix#1
Engine
Or
Previous
Channel
Biq u ad # 1 0
Output
(CxBLP)
To
Mix#2
Engine
Treble
Us er Progammable
Biquad #1 when
High-Pass Bypassed
(HPB)
User Programmable
Biquads #9 and #10
When Tone Bypassed
(CxTCB)