Datasheet

STA309A Registers

Doc ID 13855 Rev 4 33/67

Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at

the input data to each processing channel after the channel-mapping block. If any channel

receives 2048 consecutive zero value samples (regardless of fs) then that individual

channel is muted if this function is enabled.

Setting the IDE bit enables this function, which looks at the input I

S data and will

automatically mute if the signals are perceived as invalid.

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

Actively prevents double trigger of LRCLK.

When active will issue a device power down signal (EAPD) on clock loss detection

7.2.9 Configuration register I (0x08)

This feature utilizes an ADC on SDI78 that provides power supply ripple information for

correction. Registers PSC1, PSC2, PSC3 are utilized in this mode.

Table 43. IDE bit

Bit RW RST Name Description

4RW 1 IDE

Invalid input detect mute enable:

1: enable the automatic invalid input detect mute

Table 44. BCLE bit

Bit RW RST Name Description

5 RW 1 BCLE Binary output mode clock loss detection enable

Table 45. LDTE bit

Bit RW RST Name Description

6 RW 1 LDTE LRCLK double trigger protection enable

Table 46. ECLE bit

Bit RW RST Name Description

7 RW 0 ECLE Auto EAPD on clock loss

D7 D6 D5 D4 D3 D2 D1 D0

EAPD Reserved PSCE

00000000

Table 47. PSCE bit

Bit RW RST Name Description

0 RW 0 PSCE

Power supply ripple correction enable:

0: normal operation

1: PSCorrect operation