Datasheet

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October 2009 Doc ID 13855 Rev 4 1/67

STA309A

Multi-channel digital audio processor with DDX

Features

 8 channels of 24-bit DDX

(direct digital

amplification)

 >100 dB of SNR and dynamic range

 Selectable 32 kHz - 192 kHz input sample rates

 6 channels of DSD/SACD input

 Digital gain/attenuation +58 dB to -100 dB in

0.5-dB steps

 Soft volume update

 Individual channel and master gain/attenuation

plus channel trim (-10 dB to +10 dB)

 Up to 10 independent 32-bit user

programmable biquads (EQ) per channel

 Bass/treble tone control

 Pre and post EQ full 8-channel input mix on all

8 channels

 Dual independent limiters/compressors

 Dynamic range compression

 Automode™:

– 5-band graphic EQ

– 32 preset EQ curves (rock, jazz, pop, etc.)

– Automatic volume controlled loudness

– 5.1 to 2-channel downmix

– Simultaneous 5.1- and 2-channel downmix

outputs

– 3 preset volume curves

– 2 preset anti-clipping modes

– Preset movie nighttime listening mode

– Preset TV channel/commercial AGC mode

– 5.1, 2.1 bass management configurations

– 8 preset crossover filters

 Individual channel and master soft/hard mute

 Automatic zero-detect and invalid input mute

 Automatic invalid input detect mute

 Advanced PopFree operation

 Advanced AM interference frequency

switching and noise suppression modes

 I

S output channel mapping function

 Independent channel volume and DSP bypass

 Channel mapping of any input to any

processing/DDX

channel

 DC blocking selectable high-pass filter

 Selectable per-channel DDX

damped ternary

or binary PWM output

 Max power correction for lower full-power THD

 Variable per channel DDX

utput delay control

 192 kHz internal processing sample rate, 24-bit

to 36-bit precision

Description

The STA309A is a single chip solution for digital

audio processing and control in multi-channel

applications. It provides output capabilities for

DDX

. In conjunction with a DDX

power device,

the STA309A provides high-quality,

high-efficiency, all digital amplification. The device

is extremely versatile, allowing inputs of most

digital formats including 6.1/7.1-channel and

192 kHz, 24-bit DVD-audio, DSD/SACD. In 5.1

applications the additional 2 channels can be

used for audio line-out or headphone drive. In

speaker mode, with 8 channel outputs in parallel,

the STA309A can deliver more than 1 W.

Table 1. Device summary

Order code Package

STA309A TQFP64

STA309A13TR TQFP64

TQFP64

www.st.com

Summary of content (67 pages)

PAGE 1
STA309A Multi-channel digital audio processor with DDX® Features 8 channels of 24-bit DDX® (direct digital amplification) >100 dB of SNR and dynamic range Selectable 32 kHz - 192 kHz input sample rates 6 channels of DSD/SACD input TQFP64 Advanced AM interference frequency switching and noise suppression modes Digital gain/attenuation +58 dB to -100 dB in 0.
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Contents STA309A Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Thermal data . . . . . . . . . . . . . . .
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STA309A Contents 7.2.7 Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2.8 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2.9 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.10 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.11 Master volume register (0x0A) . . . . . . . . . . . . . . . .
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Contents 4/67 STA309A 7.2.44 Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2.45 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2.46 Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 47 7.2.47 Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 47 7.2.48 Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . .
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STA309A 8 Contents 7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.1 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.2 Variable max power correction . . . . . . . . . . . . . . .
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List of tables STA309A List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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STA309A List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. MV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CnV bits . . . .
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List of figures STA309A List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. 8/67 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STA309A 1 Block diagram Block diagram Figure 1. Block diagram SCL SA SDA MVO OUT1A/B LRCKI BICKI I2C SERIAL DATA IN SDI12 SDI34 OUT2A/B OUT3A/B OVERSAMPLING SYSTEM CONTROL SDI56 OUT4A/B DDX OUT5A/B OUT6A/B SDI78 OUT7A/B VARIABLE OVERSAMPLING CHANNEL MAPPING OUT8A/B TREBLE, BASS, EQ (BIQUADS) VOLUME LIMITING LRCKO SERIAL DATA OUT SYSTEM TIMING PLLB PLL XTI Figure 2.
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Pin connections Pin connections OUT1_B OUT1_A EAPD VDD GND BICKO NC LRCKO SDO_12 SDO_34 VDD GND NC SDO_56 Pin connection (top view) PWDN Figure 3.
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STA309A Pin connections Table 2. Pin Pin description (continued) Type Name Description 17 CMOS input buffer with pull-down SA Select address (I2C) 18 Bidirectional buffer: 5-V tolerant TTL schmitt trigger input; 3.3-V capable 2mA slew-rate controlled output.
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Pin connections STA309A Table 2. Pin description (continued) Pin 12/67 Type Name Description 48 3.3-V capable TTL 16mA output buffer OUT2A PWM channel 2 output A 49 3.3-V capable TTL 16mA output buffer OUT1B PWM channel 1 output B 50 3.3-V capable TTL 16mA output buffer OUT1A PWM channel 1 output A 51 3.3-V capable TTL 4mA output buffer EAPD Ext. amp power-down 55 3.3-V capable TTL 2mA output buffer BICKO Output serial clock 56 3.
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STA309A Electrical specification 3 Electrical specification 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol 3.2 Min Typ Max Unit VDD 3.3-V I/O power supply, pin VDD -0.5 - 4 V VDDA 3.3-V logic power supply, pin VDDA -0.5 - 4 V Vi Voltage on input pins -0.5 - VDD + 0.5 V Vo Voltage on output pins -0.5 - VDD + 0.3 V Tstg Storage temperature -40 - 150 °C Tamb Ambient operating temperature -40 - 90 °C Thermal data Table 4.
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Electrical specification 3.4 STA309A Electrical specifications The following specifications are valid for VDD = 3.3 V ± 0.3 V, VDDA = 3.3 V ± 0.3 V and Tamb = 0 to 70 °C, unless otherwise stated Table 6.
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STA309A 4 Pin description Pin description Master volume override (MVO) This pin enables the user to bypass the volume control on all channels. When MVO is pulled high, the master volume register is set to 0x00, which corresponds to its full scale setting. The master volume register setting offsets the individual channel volume settings, which default to 0 dB. Serial data in (SDI_12, SDI_34, SDI_56, SDI_78) Audio information enters the device here.
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I2C bus operation 5 STA309A I2C bus operation The STA309A supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization.
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I2C bus operation STA309A address and if a match is found, it acknowledges the identification on SDA bus during the 9th-bit time. The byte following the device identification byte is the internal space address. 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA309A acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA309A again responds with an acknowledgement. 5.3.
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STA309A Registers 7 Registers 7.1 Register summary Table 8.
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Registers STA309A Table 8.
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STA309A Registers Table 8.
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Registers STA309A 7.2 Register description 7.2.1 Configuration register A (0x00) 7 6 5 4 3 2 1 0 COS1 COS0 DSPB IR1 IR0 MCS2 MCS1 MCS0 1 0 0 0 0 0 1 1 Table 9. Bit MSC bits RW RST Name 0 RW 1 MCS0 1 RW 1 MCS1 2 RW 0 MCS2 Description Master clock select: selects the ratio between the input I2S sample frequency and the input clock. The STA309A supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, 192 kHz, and 2.8224 MHz DSD.
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STA309A Registers Interpolation ratio select Table 11. Bit Interpolation ratio bits RW RST Name 3 RW 0 IR0 4 RW 0 IR1 Description Interpolation ratio select: selects internal interpolation ratio based on input I2S sample frequency The STA309A has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-through).
PAGE 24
Registers 7.2.2 STA309A Configuration register B (0x01) - serial input formats D7 D6 D5 Reserved 0 0 Table 15. Bit 0 D4 D3 D2 D1 D0 SAIFB SAI3 SAI2 SAI1 SAI0 0 0 0 0 0 SAI bits RW RST Name 0 RW 0 SAI0 1 RW 0 SAI1 2 RW 0 SAI2 3 RW 0 SAI3 Description Serial audio input interface format: determines the interface format of the input serial digital audio interface.
PAGE 25
STA309A Registers The table below lists the serial audio input formats supported by STA309A as related to BICKI = 32 * fs, 48 * fs, 64 * fs, where sampling rate, fs = 32, 44.1, 48, 88.2, 96, 176.4, 192 kHz. Table 17.
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Registers 7.2.3 STA309A Configuration register C (0x02) - serial output formats D7 D6 D5 Reserved 0 0 Table 18. Bit 0 D4 D3 D2 D1 D0 SAOFB SAO3 SAO2 SAIO SAO0 0 0 0 0 0 SAO bits RW RST Name 0 RW 0 SAO0 1 RW 0 SAO1 2 RW 0 SAO2 3 RW 0 SAO3 Description Serial audio output interface format: determines the interface format of the output serial digital audio interface. The STA309A features a serial audio output interface that consists of 8 channels.
PAGE 27
STA309A Registers Table 20. SAO serial clock (continued) BICKI = BICKO SAO[3:0] Interface data format 0000 I2 0001 Left-justified data 0010 Right-justified 24-bit data 0011 Right-justified 20-bit data 0100 Right-justified 18-bit data 0101 Right-justified 16-bit data S data 64 * fs 7.2.4 Configuration register D (0x03) D7 D6 D5 D4 D3 D2 D1 D0 MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 1 0 0 0 0 1 0 Table 21.
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Registers STA309A Table 24. CSZ definition CSZ[4:0] Compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size … … 11111 31 clock period compensating pulse size Table 25. Bit MPC bit RW 7 RW RST 1 Name Description Max power correction: 1: enable STA50x correction for THD reduction near maximum power output. MPC Setting the MPC bit turns on special processing that corrects the STA50x power device at high power.
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STA309A 7.2.6 Registers Configuration register F (0x05) D7 D6 D5 D4 D3 D2 D1 D0 PWMS2 PWMS1 PWMS0 BQL PSL DEMP DRC HPB 0 0 0 0 0 0 0 0 Table 27. Bit 0 HPB bit RW RW RST 0 Name Description High-pass filter bypass bit: 1: bypass internal AC coupling digital high-pass filter HPB The STA309A features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier.
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Registers STA309A Table 30. Bit 3 PSL bit RW RW RST 0 Name Description Postscale link: 0: each channel uses individual postscale value 1: each channel uses channel 1 postscale value PSL The Postscale function can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the postscale values can be linked to the value of channel 1 for ease of use and update the values faster. Table 31.
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STA309A 7.2.7 Registers Configuration register G (0x06) D7 D6 D5 D4 D3 D2 D1 D0 MPCV DCCV HPE AM2E AME COD SID PWMD 0 0 0 0 0 0 0 0 Table 34.
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Registers STA309A Table 37. Bit DCCV bit RW 6 RW Table 38. Bit Name 0 Description Distortion compensation variable enable: 0: uses preset DC coefficient. 1: uses DCC coefficient. DCCV MPCV bit RW 7 7.2.8 RST RW RST Name 0 Description Max power correction variable: 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient MPCV Configuration register H (0x07) D7 D6 D5 D4 D3 D2 D1 D0 ECLE LDTE BCLE IDE ZDE SVE ZCE NSBW 0 1 1 1 1 1 1 0 Table 39.
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STA309A Registers Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. Table 43.
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Registers STA309A Table 48. Bit RW 7 7.2.10 EAPD bit RW RST 0 Name Description External amplifier power down: 0: external power stage power down active 1: normal operation EAPD Master mute register (0x09) D7 D6 D5 D4 D3 D2 D1 Reserved 0 7.2.11 0 0 D0 MMUTE 0 0 0 0 0 Master volume register (0x0A) D7 D6 D5 D4 D3 D2 D1 D0 MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0 1 1 1 1 1 1 1 1 Note: Value of volume derived from MVOL is dependent on AMV Automode volume settings. 7.
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STA309A 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.2.21 7.2.
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Registers 7.2.23 7.2.24 7.2.25 7.2.26 7.2.
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STA309A Registers the volume setting, the master volume setting will not affect that channel. Each channel also contains a channel mute. If CnM = 1 a soft mute is performed on that channel. Table 49. MV bits MV[7:0] Volume offset from channel value 0x00 0 dB 0x01 -0.5 dB 0x02 -1 dB … … 0x4C -38 dB … … 0xFE -127 dB 0xFF Hardware channel mute Table 50. CnV bits CnV[7:0] Volume 0x00 +48 dB 0x01 +47.5 dB 0x02 +47 dB … … 0x5F +0.5 dB 0x60 0 dB 0x61 -0.5 dB … … 0xFE -79.
PAGE 38
Registers 7.2.28 7.2.29 7.2.30 7.2.
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STA309A 7.2.32 Registers AUTO1 - Automode™ EQ, volume, GC (0x1F) D7 D6 D5 D4 D3 D2 D1 D0 AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0 0 0 0 0 0 0 0 0 Table 53. Bit 1:0 AMEQ bits RW RW RST 0 Name AMEQ[1:0] Description Biquad 2-6 mode is: 00: user programmable 01: preset EQ - PEQ bits 10: graphic EQ - xGEQ bits 11: auto volume controlled loudness curve By setting AMEQ to any setting other than 00 enables Automode EQ, biquads 1-5 are not user programmable.
PAGE 40
Registers STA309A Channels 1-6 must be arranged via channel mapping (registers CnIM) if necessary in the following manner for this operation: Channel 1: left Channel 2: right Channel 3: left surround Channel 4: right surround Channel 5: center Channel 6: LFE. 7.2.33 AUTO2 - Automode™ bass management2 (0x20) D7 D6 D5 D4 D3 D2 D1 D0 SUB RSS1 RSS0 CSS1 CSS0 FSS AMBMXE AMBMME 1 0 0 0 0 0 0 0 Table 56. Bit 0 RW RW Table 57.
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STA309A Registers Input channels must be mapped using the channel-mapping feature in the following manner for bass management to be performed properly. 1: left front 2: right front 3: left rear 4: right rear 5: center 6: LFE Table 58. CSS and RSS bits Bitfield 10 01 00 CSS - center speaker size Off Large Small RSS - rear speaker size Off Large Small Table 59.
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Registers STA309A Table 62. Bit AMAME bits RW 4 RST RW Table 63. 0 Description Automode AM enable 0: switching frequency determined by PWMS settings 1: switching frequency determined by AMAM settings AMAME AMAM bits AMAM[2:0] 7.2.35 Name 48 kHz/96 kHz input, fs 44.1 / 88.2 kHz input, fs 000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz 001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz 010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz 011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.
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STA309A Registers Table 65.
PAGE 44
Registers 7.2.36 STA309A AGEQ - graphic EQ 80-Hz band (0x23) D7 D6 D5 Reserved 0 7.2.37 0 0 D6 D5 Reserved 0 0 0 D6 D5 Reserved 0 D1 D0 AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0 0 1 1 1 1 D4 D3 D2 D1 D0 BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0 0 1 1 1 1 0 0 D4 D3 D2 D1 D0 CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0 0 1 1 1 1 DGEQ - graphic EQ 3-kHz band (0x26) D7 D6 D5 Reserved 0 7.2.40 D2 CGEQ - graphic EQ 1-kHz band (0x25) D7 7.2.
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STA309A 7.2.41 Registers Biquad internal channel loop-through (0x28) D7 D6 D5 D4 D3 D2 D1 D0 C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP 0 0 0 0 0 0 0 0 Each internal processing channel can receive two possible inputs at the input to the biquad block. The input can come either from the output of that channel’s MIX#1 engine or from the output of the bass/treble (Biquad#10) of the previous channel. In this scenario, channel 1 receives channel 8.
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Registers 7.2.43 STA309A EQ bypass (0x2A) D7 D6 D5 D4 D3 D2 D1 D0 C8EQBP C7EQBP C6EQBP C5EQBP C4EQCBP C3EQBP C2EQBP C1EQBP 0 0 0 0 0 0 0 0 EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. Table 69. Bit RW 7:0 7.2.
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STA309A 7.2.45 Registers Tone control (0x2C) D7 D6 D5 D4 D3 D2 D1 D0 TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 0 1 1 1 0 1 1 1 This is the tone control boost / cut as a function of BTC and TTC bits. Table 70. BTC and TTC bits BTC[3:0] / TTC[3:0) 7.2.46 7.2.47 7.2.
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Registers 7.2.49 7.2.50 7.2.51 7.2.
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STA309A Registers that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 7. Basic limiter and volume flow diagram Limiter RMS Attenuation Saturation Gain, volume Output Input Gain Table 71. Channel limiter mapping CnLS[1:0] Channel limiter mapping 00 Channel has limiting disabled 01 Channel is mapped to limiter #1 10 Channel is mapped to limiter #2 Table 72. Attack rate LnA[3:0] Attack rate (dB/ms) 0000 3.
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Registers STA309A Table 73. Release rate LnR[3:0] Release rate (dB/ms) 0000 0.5116 (fast) 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 (slow) Table 74.
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STA309A Registers Table 75. LnRT bits, anti-clipping Anti-clipping (AC) (dB relative to FS) LnRT[3:0] 0000 -∞ 0001 -29 dB 0010 -20 dB 0011 -16 dB 0100 -14 dB 0101 -12 dB 0110 -10 dB 0111 -8 dB 1000 -7 dB 1001 -6 dB 1010 -5 dB 1011 -4 dB 1100 -3 dB 1101 -2 dB 1110 -1 dB 1111 -0 dB Table 76.
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Registers STA309A Table 76. LnAT bits, dynamic range compression (continued) Dynamic range compression (DRC) (dB relative to volume) LnAT[3:0] 1110 -7 1111 -4 Table 77.
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STA309A 7.2.53 7.2.54 7.2.55 7.2.
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Registers 7.2.57 7.2.58 7.2.59 7.2.
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STA309A 7.2.61 Registers Coefficient address register 1 (0x3B) D7 D6 D5 0 0 0 D4 D3 D2 0 0 0 Reserved 7.2.62 7.2.63 7.2.64 7.2.65 7.2.66 7.2.
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Registers 7.2.68 7.2.69 7.2.70 7.2.71 7.2.72 7.2.73 7.2.74 7.2.
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STA309A 7.2.76 7.2.77 7.2.
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Registers 7.3 7.4 STA309A Reading a coefficient from RAM 1. write top 2-bits of address to I2C register 0x3B 2. write bottom 8-bits of address to I2C register 0x3C 3. read top 8-bits of coefficient in I2C address 0x3D 4. read middle 8-bits of coefficient in I2C address 0x3E 5. read bottom 8-bits of coefficient in I2C address 0x3F Reading a set of coefficients from RAM 1. write top 2-bits of address to I2C register 0x3B 2. write bottom 8-bits of address to I2C register 0x3C 3.
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STA309A 7.6 Registers Writing a set of coefficients to RAM 1. write top 2-bits of starting address to I2C register 0x3B 2. write bottom 8-bits of starting address to I2C register 0x3C 3. write top 8-bits of coefficient b1 in I2C address 0x3D 4. write middle 8-bits of coefficient b1 in I2C address 0x3E 5. write bottom 8-bits of coefficient b1 in I2C address 0x3F 6. write top 8-bits of coefficient b2 in I2C address 0x40 7. write middle 8-bits of coefficient b2 in I2C address 0x41 8.
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Equalization and mixing 8 STA309A Equalization and mixing Figure 8. Channel mixer CxMIX1 Channel 1 CxMIX2 Channel 2 CxMIX3 Channel 3 CxMIX4 Channel x Channel 4 CxMIX5 Channel 5 CxMIX6 Channel 6 CxMIX7 Channel 7 CxMIX8 Channel 8 8.1 Postscale The STA309A provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiply.
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STA309A Equalization and mixing Table 80.
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Equalization and mixing STA309A 8.2 Variable max power correction 8.2.1 MPCC1-2 (0x4D, 0x4E) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. D7 D6 D5 D4 D3 D2 D1 D0 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0 0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 1 1 0 0 0 0 0 0 8.
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STA309A 8.4 Equalization and mixing PSCorrect registers ADC is used to input ripple data to SDI78. The left channel (7) is used internally. No audio data can therefore be used on these channels. Though all channel mapping and mixing from other inputs to channels 7 and 8 internally are still valid. 8.4.
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Package mechanical data 9 STA309A Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 9. TQFP64 (10 x 10 x 1.4 mm) package dimensions mmmm DIM. Dimension MIN. Min A A TYP. Typ - A1 0.05 MAX. Max MIN. Min 1.60 - 0.
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STA309A 10 Trademarks and other acknowledgements Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. Automode is a trademark of Apogee Technology Inc. Dolby is a registered trademark of Dolby Laboratories. ECOPACK is a registered trademark of STMicroelectronics.
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Revision history 11 STA309A Revision history Table 81. 66/67 Document revision history Date Revision Changes Sep-2007 1 Initial release.
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STA309A Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.