Datasheet

Table 5:
PLL Configuration Sequence For
10MHz Input Clock
256 Oversapling Clock
REGISTER
ADDRESS
NAME VALUE
6 reserved 18
11 reserved 3
97 MFSDF (x) 15
80 MFSDF-441 16
101 PLLFRAC-H 169
82 PLLFRAC-441-H 49
100 PLLFRAC-L 42
81 PLLFRAC-441-L 60
5 PLLCTRL 161
Table 6:
PLL Configuration Sequence For
10MHz Input Clock
384 Oversapling Rathio
REGISTER
ADDRESS
NAME VALUE
6 reserved 17
11 reserved 3
97 MFSDF (x) 9
80 MFSDF-441 10
101 PLLFRAC-H 110
82 PLLFRAC-441-H 160
100 PLLFRAC-L 152
81 PLLFRAC-441-L 186
5 PLLCTRL 161
Table 7:
PLL Configuration Sequence For
14.31818MHz Input Clock
256 Oversapling Rathio
REGISTER
ADDRESS
NAME VALUE
6 reserved 12
11 reserved 3
97 MFSDF (x) 15
80 MFSDF-441 16
101 PLLFRAC-H 187
82 PLLFRAC-441-H 103
100 PLLFRAC-L 58
81 PLLFRAC-441-L 119
5 PLLCTRL 161
Table 8:
PLL Configuration Sequence For
14.31818MHz Input Clock
384 Oversapling Rathio
REGISTER
ADDRESS
NAME VALUE
6 reserved 11
11 reserved 3
97 MFSDF (x) 6
80 MFSDF-441 7
101 PLLFRAC-H 3
82 PLLFRAC-441-H 157
100 PLLFRAC-L 211
81 PLLFRAC-441-L 157
5 PLLCTRL 161
STA013 - STA013B - STA013T
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