Datasheet

ST8024L Functional description
Doc ID 17709 Rev 5 23/35
Figure 6. Activation sequence at t
3
6.7 Active mode
When the activation sequence is completed, the ST8024L is in its active mode. Data are
exchanged between the card and the microcontroller via the I/O lines.
The ST8024L is designed for cards without V
PP
(the voltage required to program or erase
the internal non-volatile memory).
6.8 Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit
then executes an automatic deactivation sequence by counting the sequencer back and
finishing in the inactive mode (see Figure 7):
1. RST goes low (t
10
).
2. CLK is held low (t
12
= t
10
+ 0.5 x T) where T is 64 times the period of the internal
oscillator (approximately 25 µs).
3. I/O, AUX1, and AUX2 are pulled low (t
13
= t
10
+ T).
4. V
CC
starts to fall towards zero (t
14
= t
10
+ 1.5 x T).
5. The deactivation sequence is complete at t
DE
, when V
CC
reaches its inactive state.
6. All card contacts become low impedance to GND; I/OUC, AUX1UC, and AUX2UC
remain at V
DD
(pulled-up via an 11 kΩ resistor).
7. The internal oscillator returns to its lower frequency.