Datasheet

Functional description ST8024L
18/35 Doc ID 17709 Rev 5
6 Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
6.1 Power supply
The supply pins for the ST8024L are V
DD
and GND. V
DD
should be in the range of 2.7 to
6.5 V. All signals interfacing with the system controller are referred to V
DD
, therefore V
DD
should also supply the system controller. All card reader contacts remain inactive during
power-on or power-off.
The internal circuits are kept in the reset state until V
DD
reaches V
th2
+V
HYS2
and for the
duration of the internal power-on reset pulse, t
W
(see Figure 4). When V
DD
falls below V
th2
,
an automatic deactivation of the contacts is performed.
A step-up converter is incorporated to generate the 1.8 V (for those devices with the
1.8V pin), 3 V, or 5 V card supply voltage (V
CC
). The step-up converter should be supplied
separately by V
DDP
and PGND. Due to the possibility of large transient currents, the two
100 nF capacitors of the step-up converter should be located as near as possible to the
ST8024L and have an ESR less than 350 mΩ
.
During power-up, the V
DD
supply voltage must be applied prior to the V
DDP
supply voltage
or at the same time
After powering the device, OFF
remains low until CMDVCC is set high.
During power-off, OFF
falls low when V
DD
is below the falling threshold voltage.
6.2 Voltage supervisor
6.2.1 Without external divider on pin PORADJ
The voltage supervisor surveys the V
DD
supply. A defined reset pulse of approximately 8 ms
(t
W
) is used internally to keep the ST8024L inactive during power-on or power-off of the V
DD
supply (see Figure 4).
As long as V
DD
is less than V
th2
+ V
HYS2
, the ST8024L remains inactive regardless of the
levels on the command lines. This state also lasts for the duration of t
W
after V
DD
has
reached a level higher than V
th2
+ V
HYS2
. When V
DD
falls below V
th2
, a deactivation
sequence of the contacts is performed.