Datasheet

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This is information on a product in full production.

May 2012 Doc ID 17709 Rev 5 1/35

ST8024L

Smartcard interface

Datasheet − production data

Features

■ Designed to be compatible with the NDS

conditional access system (except

ST8024LTR)

■ ISO 7816, GSM11.11 and EMV 4.2 (payment

systems) compatible

■ IC card interface

■ 3 V or 5 V supply for the ST8024L device (V

)

■ Three specifically protected half-duplex

bi-directional buffered I/O lines to card contacts

C4, C7 and C8

■ Step-up converter for V

generation

separately powered by a 5 V ± 20% supply

DDP

and PGND)

■ 1.8 V ± 6.5%, 3 V or 5 V ± 5% regulated card

supply voltage (V

) with appropriate

decoupling has the following capabilities:

–I

< 80 mA at V

DDP

= 4.75 to 6.5 V

– Handles current spikes of 40 nA up

to 20 MHz

– Controls rise and fall times

– Filtered overload detection at ~120 mA

■ Thermal and short-circuit protection on all card

contacts

■ Automatic activation and deactivation

sequences; initiated by software or by

hardware in the event of a short-circuit, card

take-off, overheating, V

or V

DDP

dropout

■ Enhanced ESD protection on card side (>6 kV)

■ 26 MHz integrated crystal oscillator

■ Built-in debounce on card presence contacts

■ One multiplexed status signal OFF

■ Non-inverted control of RST via pin RSTIN

■ Clock generation for cards up to 20 MHz

(divided by 1, 2, 4 or 8 through CLKDIV1 and

CLKDIV2 signals) with synchronous frequency

changes

■ Supply supervisor for spike-killing during

power-on and power-off and power-on reset

(threshold fixed internally or externally by

a resistor divider)

Applications

■ Smartcard readers for set-top boxes

■ IC card readers for banking

■ Identification, pay TV

SO-28

TSSOP-28

TSSOP-20

Table 1. Device summary

Order code

PORADJ/

1.8 V function

Temperature

range

Package Packaging

Package

top mark

ST8024LCDR

(1)

PORADJ –25 to 85 °C SO-28 (tape and reel) 1000 parts per reel ST8024LC

ST8024LCTR

(1)

PORADJ –25 to 85 °C TSSOP-28 (tape and reel) 2500 parts per reel ST8024LC

ST8024LACDR

(1)

1.8 V –25 to 85 °C SO-28 (tape and reel) 1000 parts per reel ST8024LAC

ST8024LTR 1.8 V –25 to 85 °C TSSOP-20 (tape and reel) 2500 parts per reel ST8024L

ST8024LACTR

(1)

1.8 V –25 to 85 °C TSSOP-28 (tape and reel) 2500 parts per reel ST8024LAC

1. Certified by NDS.

www.st.com

Summary of content (35 pages)

PAGE 1
ST8024L Smartcard interface Datasheet − production data Features ■ Designed to be compatible with the NDS conditional access system (except ST8024LTR) ■ ISO 7816, GSM11.11 and EMV 4.
PAGE 2
Contents ST8024L Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
ST8024L List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . .
PAGE 4
List of figures ST8024L List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. 4/35 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
ST8024L 1 Description Description The ST8024L is a complete low-cost analog interface for asynchronous Class A, B, and C smartcards. It can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. The ST8024LCDR and ST8024LCTR are compatible with the ST8024 (with the exception of Vth(ext)rise/fall value).
PAGE 6
Diagram ST8024L 2 Diagram Figure 1. Block diagram 6$$0 0'.$ 6$$ N& N& N& # n # 3500,9 34%0 50 #/.6%24%2 6$$ ).4%2.!, 2%&%2%.#% 2 6REF ).4%2.!, /3#),,!4/2 -(Z 6/,4!'% 3%.3% 0/2!$* 6 2 N& #,+50 0/7%2?/. /&& 234). #-$6## %. 06## 6 6 6 %. 6$$ #,+$)6 #,+$)6 %. !,!2- 650 84!, 84!, (/23%1 3%15%.#%2 '%.%2!4/2 #,/#+ "5&&%2 #,+ 234 "5&&%2 %.
PAGE 7
ST8024L Pin configuration 3 Pin configuration Figure 2. Pin connections Table 2. Pin description Symbol Name and function SO-28/ TSSOP-28 TSSOP-20 CLKDIV1 Control of CLK frequency (internal 11 kΩ pull-up resistor connected to VDD) 1 N. A. CLKDIV2 Control of CLK frequency (internal 11 kΩ pull-down resistor connected to GND) 2 N. A. 5V/3V 5 V or 3 V VCC selection for communication with the smartcard.
PAGE 8
Pin configuration Table 2. ST8024L Pin description (continued) Symbol Name and function SO-28/ TSSOP-28 TSSOP-20 AUX2 Auxiliary line to and from card (C8) (internal 11 kΩ pull-up resistor connected to VCC) 12 N. A. AUX1 Auxiliary line to and from card (C4) (internal 11 kΩ pull-up resistor to VCC) 13 N.
PAGE 9
ST8024L Maximum ratings 4 Maximum ratings Table 3. Absolute maximum ratings(1) Symbol Parameter Min. Max. Unit -0.3 7 V VDD, VDDP Supply voltage Vn1 Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2, PORADJ/1.8V, CMDVCC, PRES, PRES, and OFF -0.3 VDD + 0.3 V Vn2 Voltage on card contact pins I/O, RST, AUX1, AUX2, and CLK -0.3 VCC + 0.
PAGE 10
Electrical characteristics ST8024L 5 Electrical characteristics Table 6. Electrical characteristics over recommended operating condition Symbol VDD VDDP IDD IDDP Parameter(1) Test conditions Supply voltage Supply voltage for the step-up converter Min. Typ. 2.7 Max. Unit 6.5 V VCC = 5 V; |ICC| < 80 mA 4.0 5 6.5 VCC = 3 V; |ICC| < 65 mA 4.0 5 6.5 VCC = 5 V; |ICC| < 20 mA 3.0 6.5 VCC = 3 V; |ICC| < 20 mA 2.7 6.5 VCC = 1.8 V; |ICC| < 20 mA 2.7 6.5 Card inactive 1.
PAGE 11
ST8024L Table 7. Symbol fCLK Vth(vd-vf) VUP Electrical characteristics Step-up converter Parameter(1) Test conditions Min. Typ. Max. Unit 3.2 MHz Clock frequency Card active 2.2 Threshold voltage for step-up converter to change to voltage follower 5 V card 5.2 5.8 6.2 3 V card 3.8 4.1 4.4 1.8 V card 3.8 4.1 4.4 5 V card 5.2 5.7 6.2 3 V card 3.5 3.9 4.3 1.8 V card 3.5 3.9 4.3 Typ. Max. Unit 400 nF Output voltage on pin VUP (average value) V V 1. VDD = 3.
PAGE 12
Electrical characteristics Table 8. Symbol |ICC| ST8024L Card supply voltage characteristics (continued) Parameter(1) Card supply current Test conditions Slew rate Typ. Max. VCC = 0 to 5 V 80 VCC = 0 to 3 V 65 VCC = 0 to 1.8 V 45 Unit mA VCC short-circuit to GND SR Min. Slew up or down, VCC = 5 V; 3 V; 1.8 V; |ICC| < 30 mA 90 0.08 120 0.15 0.22 V/µs 1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
PAGE 13
ST8024L Table 11. Symbol Electrical characteristics Data lines to card reader (pins I/O, AUX1, and AUX2 with integrated 11 kΩ pull-up resistor to VCC) Parameter(1) Test conditions No load VO(inactive) Output voltage Inactive mode IO(inactive) Output current Inactive mode; pin grounded High level output voltage Typ. 0 Max. Unit 0.1 V IO(inactive) = 1 mA No DC load VOH Min. 0.3 -1 0.9 VCC VCC +0.1 5 V and 3 V cards; IOH < –40 µA 0.75 VCC VCC +0.1 1.8 V card IOH < –40 µA 0.
PAGE 14
Electrical characteristics Table 12. Symbol VOH ST8024L Data lines to microcontroller (pins I/OUC, AUX1UC, and AUX2UC with integrated 11 kΩ pull-up resistor to VDD) Parameter(1) High level output voltage Test conditions Min. Typ. Max. Unit 5 V, 3 V and 1.8 V cards; IOH < –40 µA 0.75 VDD VDD +0.1 No DC load 0.9 VDD VDD +0.1 IOL = 1 mA 0 0.3 V V VOL Low level output voltage VIH High level input voltage 0.7 VDD VDD +0.3 V VIL Low level input voltage -0.3 0.
PAGE 15
ST8024L Table 15. Symbol VO(inactive) Electrical characteristics Clock output to card reader (pin CLK) Parameter(1) Output voltage in inactive mode IO(inactive) Output current VOL Low level output voltage VOH High level output voltage tR, tF Rise and fall time δ SR Test conditions Min. Typ. Max. IO(inactive) = 1 mA 0 - 0.3 No load 0 - 0.1 CLK inactive mode; pin grounded 0 - –1 IOL = 200 µA 0 - 0.3 IOL = 70 mA (current limit) VCC -0.4 - VCC IOH = –200 µA 0.
PAGE 16
Electrical characteristics Table 17. Symbol ST8024L Card presence inputs (pins PRES and PRES) Parameter(1) Test conditions Min. Typ. Max. Unit VIL Low level input voltage -0.3 - 0.3 VDD V VIH High level input voltage 0.7 VDD - VDD +0.3 V |ILIH| High level input leakage current VIH = VDD - 5 µA |ILIL| Low level input leakage current VIL = 0 - 5 µA 1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted.
PAGE 17
ST8024L Figure 3.
PAGE 18
Functional description 6 ST8024L Functional description Throughout this document it is assumed that the reader is familiar with ISO7816 terminology. 6.1 Power supply The supply pins for the ST8024L are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All signals interfacing with the system controller are referred to VDD, therefore VDD should also supply the system controller. All card reader contacts remain inactive during power-on or power-off.
PAGE 19
ST8024L Functional description Figure 4. 6.2.2 Voltage supervisor With an external divider on pin PORADJ In this case, a resistor divider is connected to the PORADJ pin (see Figure 1). Vth(ext) rise and Vth(ext) fall are the external rising threshold voltage and the external falling threshold voltages on pin PORADJ that switch the device on and off.
PAGE 20
Functional description 6.3 ST8024L Clock circuitry (only on SO-28 and TSSOP-28 packages) The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2. The clock frequency can be fXTAL, 1/2 x fXTAL, 1/4 x fXTAL, or 1/8 x fXTAL. Frequency selection is made via inputs CLKDIV1 and CLKDIV2 (see Table 21). Table 21.
PAGE 21
ST8024L 6.4 Functional description I/O transceivers The three data lines I/O, AUX1, and AUX2 are identical. The idle state is realized by both I/O and I/OUC lines being pulled high via an 11 kΩ resistor (I/O to VCC and I/OUC to VDD). Pin I/O is referenced to VCC, and pin I/OUC to VDD, therefore allowing operation when VCC is not equal to VDD. The first side of the transceiver to receive a falling edge becomes the master.
PAGE 22
Functional description ST8024L The clock may be applied to the card using the following sequence (see Figure 5): 1. Set RSTIN high. 2. Set CMDVCC low. 3. Reset RSTIN low between t3 and t5; CLK starts at this moment. 4. RST remains low until t5, when RST is enabled to be the copy of RSTIN. 5. After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK pulses before toggling RST. If the applied clock is not needed, then CMDVCC may be set low with RSTIN low.
PAGE 23
ST8024L Functional description Figure 6. Activation sequence at t3 6.7 Active mode When the activation sequence is completed, the ST8024L is in its active mode. Data are exchanged between the card and the microcontroller via the I/O lines. The ST8024L is designed for cards without VPP (the voltage required to program or erase the internal non-volatile memory). 6.8 Deactivation sequence When a session is completed, the microcontroller sets the CMDVCC line HIGH.
PAGE 24
Functional description Figure 7. Deactivation sequence 6.9 VCC generator ST8024L The VCC generator has a capacity to supply up to 80 mA (max.) continuously at 5 V, 65 mA (max.) at 3 V, and 45 mA (max.) at 1.8 V. An internal overload detector operates at approximately 120 mA. Current samples to the detector are internally filtered, allowing spurious current pulses up to 200 mA with a duration in the order of µs to be drawn by the card without causing deactivation.
PAGE 25
ST8024L 6.10 Functional description Fault detection The following fault conditions are monitored: ● Short-circuit or high current on VCC ● Removal of a card during a transaction ● VDD dropping ● Step-up converter operating out of the specified values (VDDP too low or current from VUP too high) ● Overheating ● There are two different cases (see Figure 8): – CMDVCC high outside a card session. Output OFF is low if a card is not in the card reader, and high if a card is in the reader.
PAGE 26
Functional description Figure 9. 6.11 ST8024L Emergency deactivation sequence (card extraction) VCC selection settings The ST8024L supports three smartcard VCC voltages: 1.8 V, 3 V, and 5 V. The VCC selection is controlled by the 1.8V and 5V/3V signals as shown in Table 23. The 1.8V signal has priority over the 5V/3V. When the 1.8 V pin is taken high, VCC is 1.8 V and it overrides any setting on the 5V/3V pin. When the 1.8V pin is taken low, the 5V/3V pin selects the 5 V or 3 V VCC.
PAGE 27
ST8024L 7 Applications Applications Figure 10. Hardware hookup 1. These capacitors must be < 350 mΩ ESR and be placed near the IC (within 10 mm). 2. ST8024L and the microcontroller must use the same VDD supply. 3. Make short, straight connections between CGND, C5, and the ground connection to the capacitor. 4. Mount one ESR-type (< 350 mΩ) 100 nF capacitor close to pin VCC. 5. Mount one ESR-type (< 350 mΩ) 100 nF capacitor close to C1 contact. 6.
PAGE 28
Package mechanical data 8 ST8024L Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 11. SO-28 small outline, package mechanical drawing 0016572_F Table 24. SO-28 small outline, package mechanical data Dimensions Symbol mm. Min. Typ.
PAGE 29
ST8024L Package mechanical data Figure 12. TSSOP-20 package mechanical drawing A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 Table 25. 0087225_D TSSOP-20 package mechanical data Dimensions Symbol mm. Min. Typ. A inches Max. Min. Typ. 1.2 A1 0.05 A2 0.8 b Max. 0.047 0.15 0.002 1.05 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 1 0.
PAGE 30
Package mechanical data ST8024L Figure 13. TSSOP-28 package mechanical drawing 0128292_D Table 26. TSSOP-28 package mechanical data Dimensions Symbol mm. Min. Typ. A Max. Min. Typ. 1.2 A1 0.05 A2 0.8 b Max. 0.047 0.15 0.002 1.05 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 9.6 9.7 9.8 0.378 0.382 0.386 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 30/35 inches 1 0.65 BSC K 0° L 0.45 0.60 0.006 0.039 0.041 0.
PAGE 31
ST8024L Package mechanical data Figure 14. SO-28 tape and reel schematic Note: Drawing is not to scale. Table 27. SO-28 tape and reel mechanical data Dimensions Symbol mm. Min. A Typ. inches Max. Min. 330 Max. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 Typ. 0.504 30.4 0.519 1.197 AO 10.8 11.0 0.425 0.433 BO 18.2 18.4 0.716 0.724 KO 2.9 3.1 0.114 0.122 PO 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.
PAGE 32
Package mechanical data ST8024L Figure 15. TSSOP-20 tape and reel schematic Note: Drawing is not to scale. Table 28. TSSOP-20 tape and reel mechanical data Dimensions Symbol mm. Min. A Max. Min. 330 13.2 Typ. Max. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 32/35 Typ. inches 0.504 22.4 0.519 0.882 AO 6.8 7 0.268 0.276 BO 6.9 7.1 0.272 0.280 KO 1.7 1.9 0.067 0.075 PO 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.
PAGE 33
ST8024L Package mechanical data Figure 16. TSSOP-28 tape and reel schematic Note: Drawing is not to scale. Table 29. TSSOP-28 tape and reel mechanical data Dimensions Symbol mm. Min. A Typ. inches Max. Min. 330 Max. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 Typ. 0.504 22.4 0.519 0.882 AO 6.8 7 0.268 0.276 BO 10.1 10.3 0.398 0.406 KO 1.7 1.9 0.067 0.075 PO 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.
PAGE 34
Revision history ST8024L 9 Revision history Table 30. Document revision history Date Revision 19-Jul-2010 1 Initial release. 30-Jul-2010 2 Updated Description, Table 6. 27-Sep-2010 3 Updated Features, Table 1, 6, 8, 19, 20, Section 6.1, Section 6.2.2, Section 6.6, Section 6.9, footnotes of Figure 10. 4 Added ST8024LACTR device, updated Features, Table 1, Section 1: Description (moved to page 5), Figure 1,Figure 2, Table 2, Table 6,Table 8, Section 6.1 to Section 6.
PAGE 35
ST8024L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.