Datasheet

ST8024 Functional description
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5.7 Active mode
When the activation sequence is completed, the ST8024 will be in its active mode. Data are
exchanged between the card and the microcontroller via the I/O lines.
The ST8024 is designed for cards without V
PP
(the voltage required to program or erase the
internal non-volatile memory).
5.8 Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit
then executes an automatic deactivation sequence by counting the sequencer back and
finishing in the inactive mode (see Figure 7):
1. RST goes LOW (t
10
).
2. CLK is held LOW (t
12
= t
10
+ 0.5 x T) where T is 64 times the period of the internal
oscillator (approximately 25 µs).
3. I/O, AUX1 and AUX2 are pulled LOW (t
13
= t
10
+ T).
4. V
CC
starts to fall towards zero (t
14
= t
10
+ 1.5 x T).
5. The deactivation sequence is complete at t
de
, when V
CC
reaches its inactive state.
6. V
UP
falls to zero (t
15
= t
10
+ 5T) and all card contacts become low-impedance to GND;
I/OUC, AUX1UC and AUX2UC remain at V
DD
(pulled-up via a 11 kΩ resistor).
7. The internal oscillator returns to its lower frequency.
Figure 7. Deactivation sequence
5.9 V
CC
generator
The V
CC
generator has a capacity to supply up to 80 mA continuously at 5 V and 65 mA at 3
V. An internal overload detector operates at approximately 120 mA. Current samples to the