Datasheet

ST7540 Auxiliary analog and digital functions

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7.3 Reset & watchdog

RSTO Output is a reset generator for the application circuitry. During the ST7540 startup

sequence is forced low. RSTO becomes high after a T

RSTO

delay from the end of oscillator

startup sequence.

Inside ST7540 is also embedded a watchdog function. The watchdog function is used to

detect the occurrence of a software fault of the Host Controller. The watchdog circuitry

generates an internal and external reset (RSTO low for T

RSTO

time) on expiry of the internal

watchdog timer. The watchdog timer reset can be achieved applying a negative pulse on

WD pin (see Figure 23).

Figure 23. Reset and Watchdog Timing

7.4 Output clock

MCLK is the master clock output. The clock frequency sourced can be programmed through

the Control Register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4).

The transition between one frequency and another is done only at the end of the ongoing

cycle. The oscillator can be disabled using Control Register bits 15 and 16 (Tabl e 1 2).

7.5 Output voltage level freeze

The Output Level Freeze function, when enabled, turns off the Voltage Control Loop once

the ALC stays in a stable condition for about 3 periods of control loop, and maintains a

constant gain until the end of transmission. Output Level Freeze can be enabled using

Control Register bit 17 (Ta bl e 1 2). This function is available only using the Extended Control

7.6 Extended control register

When Extended Control Register function is enabled, all the 48 bits of Control Register are

programmable. Otherwise, only the first 24 bits of Control Register are programmable. The

functions Header Recognition, Frame Bit Count and Output Voltage Freeze are available

only if Extended Control Register function is enabled. Extended Control Register can be

enabled using Control Register bit 21(Tabl e 1 2 ).

RSTO

D03IN1410