Datasheet

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September 2006 Rev 2 1/44

ST7540

FSK power line transceiver

General features

■ Half-duplex frequency shift keying (FSK)

transceiver

■ Integrated power line driver with programmable

voltage and current control

■ Programmable mains access:

– Synchronous

– Asynchronous

■ Single supply voltage (from 7.5V up to 13.5V)

■ Very low power consumption (I

= 5mA)

■ Integrates 5V voltage regulator (up to 50mA)

with short circuit protection

■ Integrated 3.3V voltage regulator (up to 50mA)

with short circuit protection

■ 3.3V or 5V digital supply

■ 8 Programmable transmission frequencies

■ Programmable baud rate up to 4800BPS

■ Receiving sensitivity up to 250µV

RMS

■

Suitable for applications in accordance with EN

50065 Cenelec specification

■ Carrier or preamble detection

■ Band in use detection

■ Programmable control register

■ Watchdog timer

■ 8 or 16 Bit header recognition

■ ST7537 and ST7538 compatible

■ UART/SPI host interface

Description

The ST7540 is a Half Duplex

synchronous/asynchronous FSK Modem

designed for power line communication network

applications. It operates from a single supply

voltage and integrates a line driver and two linear

regulators for 5V and 3.3V. The device operation

is controlled by means of an internal register,

programmable through the synchronous serial

interface. Additional functions as watchdog, clock

output, output voltage and current control,

preamble detection, time-out and band in use are

included. Realized in Multipower BCD5

technology that allows to integrate DMOS, Bipolar

and CMOS structures in the same chip.

HTSSOP28 Exposed Pad

www.st.com

Order codes

Part number Package Packaging

ST7540 HTSSOP28 (Exposed Pad) Tube

ST7540TR HTSSOP28 (Exposed Pad) Tape and reel

Summary of content (44 pages)

PAGE 1
ST7540 FSK power line transceiver General features ■ Half-duplex frequency shift keying (FSK) transceiver ■ Integrated power line driver with programmable voltage and current control ■ Programmable mains access: – Synchronous – Asynchronous HTSSOP28 Exposed Pad ■ Single supply voltage (from 7.5V up to 13.5V) ■ Very low power consumption (Iq = 5mA) ■ Integrates 5V voltage regulator (up to 50mA) with short circuit protection ■ Integrated 3.
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Contents ST7540 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . .
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ST7540 7 Contents Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 Output clock . . . . . . . . . . . . . . . . . . .
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Block diagram ST7540 1 Block diagram Figure 1.
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ST7540 Pin settings 2 Pin settings 2.1 Pin connection Figure 2. 2.2 Pin connection (top view) CD_PD 1 28 TEST2 REG_DATA 2 27 TEST1 GND 3 26 VDC RxD 4 25 RX_IN RxTx 5 24 CL TxD 6 23 Vsense BU/THERM 7 22 X2 CLR/T 8 21 X1_OSCIN VDD 9 20 SVSS MCLK 10 19 TX_OUT RSTO 11 18 PA_IN+ UART/SPI 12 17 VCC WD 13 16 VSS PA_IN- 14 15 PA_OUT Pin description Table 1.
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Pin settings ST7540 Table 1. Pin description (continued) N° 7 Name Type BU/THERM Digital/Output Band in use/Thermal Shutdown event detection output. In Rx mode: "1" Signal within the programmed band "0" No signal within the programmed band In Tx mode: "1" - Thermal Shutdown event occurred "0" - No Thermal Shutdown event occurred (signal not latched) 8 CLR/T Digital/Output Synchronous mains access clock or control register access clock 9 VDD Supply/Power Digital supply voltage or 3.
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ST7540 Electrical data 3 Electrical data 3.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VCC Power supply voltage -0.3 to + 14 V VDD Digital supply voltage -0.3 to +5.5 V Voltage between SVSS and GND -0.3 to +0.3 V Digital input voltage GND - 0.3 to VDD +0.3 V VO Digital output voltage GND - 0.3 to VDD +0.3 V IO Digital output current -2 to +2 mA SVSS - 0.3 to 5.6 V -5.6 to 5.6 V SVSS - 0.3 to 5.6 V VSS - 0.3 to +VCC +0.
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Electrical data 3.3 ST7540 Recommended operating conditions Table 4. Recommended operating conditions Symbol Parameter Value Unit 100 V/ms VCC Max allowed slope during Power-up I(VCC) Powered analog supply Current with digital supply provided externally Maximum total current 650 mArms Maximum voltage Difference between VCC VCC - VDD and VDD during power-up sequence VDD < 4.75V with 5V Digital supply provided externally 1.2 V VCC-4.
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ST7540 4 Electrical characteristics Electrical characteristics Table 5. Electrical characteristics ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C, unless otherwise specified) Symbol Parameter VDD Digital supply voltages VCC Power supply voltage I(VDD) Digital input supply current I(VCC) Power supply current current with digital supply provided externally UVLO Under voltage lock out Threshold on VCC UVLOHYS Test condition Min. Typ. Max. Unit 4.75 5 5.
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Electrical characteristics ST7540 Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C, unless otherwise specified) Symbol Parameter Test condition VOH High logic level output voltage IOH= -2mA VOL Low logic level output voltage IOL= 2mA Min. Typ. Max. VDD 0.75 Unit V GND + 0.4 V Oscillator External Clock X2 voltage swing External clock. Figure 4 5 Vpp External Clock X2 DC voltage level External clock. Figure 4 2.
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ST7540 Electrical characteristics Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C, unless otherwise specified) Symbol VSENSE Parameter Test condition Min. VSENSE Input impedance Typ. Max. 36 Unit kΩ Current control loop reference threshold on Figure 17 CL pin 1.80 1.90 2.00 V Hysteresis on current loop reference threshold 210 250 290 mV Figure 21 - 600 Baud Xtal = 16MHz 1.
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Electrical characteristics ST7540 Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C, unless otherwise specified) Symbol HD2PA_OUT HD3PA_OUT Parameter Test condition Min. Typ. Max. Unit Second harmonic distortion on PA_OUT VPA_OUT = 5.6VPP , VCC = 12V RLOAD = 30Ω Carrier frequency: 86KHz Figure 3 -63 dBc Third harmonic distortion on PA_OUT pin VPA_OUT = 5.
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ST7540 Electrical characteristics Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C, unless otherwise specified) Symbol Parameter Test condition Min. Typ. Max. Unit Linear regulator output 0 < Io < 50mA 7.5V < VCC < 13.5V voltage -5% 5.05 +5% V -5% 3.3 +5% V 5V Voltage regulator VDC 3.3V Voltage regulator VDD Linear regulator output 0 < Io < 50mA 7.5V < VCC < 13.
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Electrical characteristics ST7540 Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C, unless otherwise specified) Symbol Parameter Test condition Min. Typ. Max. Unit Serial Interface 1667 833 417 208 TB Baud rate Bit Time (1/BAUD) Control register bit 3 and bit 4 (See Figure 13) Ts Setup time see Figures 8, 9, 10, 11 & 12 5 ns TH Hold time see Figures 8, 9, 10, 11 & 12 2 ns TCR CLR/T vs.
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ST7540 Crystal resonator and external clock External clock waveform X2 SVss Figure 5. External ClockOFFSET Figure 4.
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Functional description ST7540 6 Functional description 6.1 Carrier frequencies ST7540 is a multi frequency device: eight programmable Carrier Frequencies are available (see Table 6). Only one Carrier can be used a time. The communication channel could be varied during the normal working Mode to realize a multi frequency communication. Selecting the desired frequency in the Control Register the Transmission and Reception filters are accordingly tuned. Table 6.
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ST7540 6.3 Functional description Mark and space frequencies Mark and Space Communication Frequencies are defined by the following formula: F ("0") = FCarrier + [∆F]/2 F ("1") = FCarrier - [∆F]/2 ∆F is the Frequency Deviation. With Deviation = “0.5” the difference in terms of frequency between the mark and space tones is half the Baudrate value (∆F=0.5*BAudrate). When the Deviation = “1” the difference is the Baudrate itself (∆F= Baudrate). The minimal Frequency Deviation is 600Hz. Table 8.
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Functional description ST7540 Table 8. ST7540 synthesized frequencies -- -600 600 1 75684 76335 0.5 75684 76335 1200 132161 132813 0.5 132161 132813 1 131836 133138 0.5 131836 133138 1 131348 133626 0.5 131348 133626 1 130046 134928 1200 1 75358 76660 132.5 76 0.5 75358 76660 2400 2400 1 74870 77148 0.5 74870 77148 4800 4800 1 6.
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ST7540 6.5 Functional description Host processor interface ST7540 exchanges data with the host processor through a serial interface. The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged using RxD, TxD and CLR/T lines. Four are the ST7540 working modes: ● Data Reception ● Data Transmission ● Control Register Read ● Control Register Write REG_DATA and RxTx lines are level sensitive inputs. Table 9.
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Functional description Figure 6.
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ST7540 Functional description ● Synchronous mode: In Synchronous Mode ST7540 is always the master of the communication and provides the clock reference on CLR/T line. When ST7540 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge. When ST7540 is in transmitting mode the clock reference is internally generated and TxD line is sampled on CLR/T rising Edge.
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Functional description 6.5.2 ST7540 Control register access The communication with ST7540 Control Register is always synchronous. The access is achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus REG_DATA Line. With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control Register MSB first. The ST7540 samples the TxD line on CLR/T rising edges. The control Register content is updated at the end of the register access section (REG_DATA falling edge).
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ST7540 Functional description Figure 11. Data transmission ➨ control register read ➨ data reception timing diagram TCC TCC CLR_T TB TDS RxD BIT23 TDH TDH BIT22 TCR REG_DATA TDS TCR TCR RxTx TSTH TxD D03IN1405 Figure 12. Data transmission ➨ control register write ➨ data reception timing diagram TCC TCC CLR_T TB TSTH TxD BIT23 BIT22 TCR TSTH REG_DATA TCR TCR RxTx TDS TDH RxD D03IN1401 6.6 Receiving mode The receive section is active when RxTx Pin =”1” and REG_DATA=0.
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Functional description ST7540 ● Receiving Sensitivity Level Selection It is possible to select the ST7540 Receiving Sensitivity Level by Control Register (see Table 12) or setting to ‘1’ the TxD pin during reception phase (this condition overcomes the control register setting the sensitivity equal to BU threshold). Increasing the device sensitivity allows to improve the communication reliability when the ST7540 sensitivity is the limiting factor.
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ST7540 Functional description ● Carrier Detection The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RX_IN Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode).
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Functional description ST7540 Figure 14. CD_PD Timing during RX TDCD TCD TDCD TCD CD_PD RX_IN demodulation active on RxD pin noise demodulated RxD (UART/SPI="1") noise demodulated RxD (UART/SPI="0") D03IN1418 Figure 15. Receiving path block diagram Bits 3-4 RxD MIXER 4 CLR/T PLL Bits 18-21 & 24-47 CD_PD 1 Low Pass DIGITAL FILTER Bits 9-10 HEADER RECOGN.
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ST7540 Functional description In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. The transition between a symbol and the following is done at the end of the on-going half FSK sinewave cycle. Figure 16.
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Functional description ST7540 The Current control loop acts to limit the maximum Peak Output current inside PA_OUT. The current control loop acts through the voltage control loop decreasing the Output Peak-to-Peak Amplitude to reduce the Current inside the Power Line Interface. The current sensing is done by mirroring the current in the High side MOS of the Power Amplifier (not dissipating current Sensing).
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ST7540 Functional description Table 11. VOUT Vs. R1 & R2 resistors value Note: Vout (Vrms) Vout (dBµV) (R1+R2)/R2 R2 (KΩ) R1 (KΩ) 0.150 103.5 1.1 7.5 1.0 0.250 108.0 1.9 5.1 3.9 0.350 110.9 2.7 3.6 5.6 0.500 114.0 3.7 3.3 8.2 0.625 115.9 4.7 3.3 11.0 0.750 117.5 5.8 2.7 12.0 0.875 118.8 6.6 2.0 11.0 1.000 120.0 7.6 1.6 10.0 1.250 121.9 9.5 1.6 13.0 1.500 123.5 10.8 1.6 15.
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Functional description ST7540 Figure 19. PA_OUT and VCC relationship V Vcc ≤ 3V VPA_OUT(AC) ≤ 1.5V VPA_OUT(DC) Vss t D03IN1425 Inputs and outputs of PA are available on pins PA_IN-,PA_IN+ and PA_OUT. User can easily select an appropriate active filtering topology to filter the signal present on TX_OUT pin. TX_OUT output has a current capability much lower than PA_OUT.
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ST7540 Functional description Figure 20. Power line interface topology Vcc Z2 PA_IN- - Z1 PA_OUT + PA_IN+ AC LINE R3 TX_OUT ALC R4 Vss R1 VOLTAGE LOOP Vsense CURRENT LOOP CL R2 RCL 80pF typ. D03IN1422 Figure 21. Power line interface startup timing diagram RxTx TALC TRXTX TST 2.
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Functional description 6.8 ST7540 Control register The ST7540 is a multi-channel and multifunction transceiver. An internal 24 or 48 Bits (in Extended mode) Control Register allows to manage all the programmable parameters (Table 12).
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ST7540 Functional description Table 12. Control register functions Function 0 to 2 3 to 4 Frequencies Baud rate Value 60 KHz 66 KHz 72 KHz 76 KHz 82.05 KHz 86 KHz 110 KHz 132.5 KHz 600 1,200 2,400 4,800 Selection Note Bit2 Bit1 Bit0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bit 4 Bit 3 0 0 1 1 0 1 0 1 Default 132.5 kHz 2400 Bit 5 5 Deviation 0.5 1 0 1 0.
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Functional description ST7540 Table 12. Control register functions Function Value Selection Bit 13 Preamble detection without conditioning Preamble detection with conditioning 12 to 13 Carrier detection with conditioning Default Bit 12 0 0 0 Preamble detection notification on CD_PD Line CLR/T and RxD signal always present In UART Mode (UART/SPI pin set to 1) this configuration is not allowed. 1 Preamble Detection notification on CD_PD Line.
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ST7540 Functional description Table 12.
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Auxiliary analog and digital functions ST7540 7 Auxiliary analog and digital functions 7.1 Band in use The Band in Use Block has a Carrier Detection like function but with a different Input Sensitivity (83.5 dBµV Typ.) and with a different BandPass filter Selectivity (40dB/Dec). BU/THERM line is forced High when a signal in band is detected. To prevent BU/THERM line false transition, Band in Use signal is conditioned to Carrier Detection Internal Signal.
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ST7540 7.3 Auxiliary analog and digital functions Reset & watchdog RSTO Output is a reset generator for the application circuitry. During the ST7540 startup sequence is forced low. RSTO becomes high after a TRSTO delay from the end of oscillator startup sequence. Inside ST7540 is also embedded a watchdog function. The watchdog function is used to detect the occurrence of a software fault of the Host Controller.
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Auxiliary analog and digital functions 7.7 ST7540 Under voltage lock out The UVLO function turns off the device if the VCC voltage falls under 4V. Hysteresis is 340mV typically. 7.8 Thermal shutdown The ST7540 is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170°C ±10% . Hysteresis is around 30°C. When shutdown threshold is overcome, PLI interface is switched OFF. Thermal Shutdown event is notified to the HOST controller using BU/THERM line.
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ST7540 Auxiliary analog and digital functions Figure 24. Power-up sequence Voltage 5V/3.
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/44 HOST CONTROLLER 5V Supply for Host Controller Clock & Reset for Host Controller RSTO MCLK 5 Lines Serial Interface REG/DATA CLR/T RxTx TxD RxD CD/PD BU/THERM WD TEST1 TEST2 VDD VDC 11 10 2 8 5 6 4 1 7 13 27 28 9 26 GND 3 ST7540 UART/SPI 12 SVss 20 21 22 24 23 16 19 25 18 15 14 17 X1_OSCIN X2 RCL CL Vsense VSS TX_OUT RX_IN PA_IN+ PA_OUT PA_IN- VCC R4 R3 Voltage Regulation & Current Protection D03IN1412A Z1 Z2 C1 AC/DC Converter R2 R
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ST7540 8 Mechanical data Mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.
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Mechanical data ST7540 Table 13. HTSSOP28 Mechanical data mm. inch Dim. Min. Typ. Min. Typ. Max. A 1.2 0.047 A1 0.15 0.006 A2 0.8 1.05 0.031 b 0.19 0.3 0.007 0.012 c 0.09 0.2 0.003 0.008 D (*) 9.6 9.8 0.377 D1 3.3 E 6.2 6.4 6.6 E1 (*) 4.3 4.4 4.5 E2 1.5 e L L1 1.0 9.7 aaa 0.041 0.382 0.385 0.244 0.252 0.260 0.169 0.173 0.177 0.65 0.45 0.039 0.130 0.6 0.026 0.75 0.018 1.0 k 0.024 0.039 0° (min), 8° (max) 0.1 Figure 26.
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ST7540 9 Revision history Revision history Table 14. Revision history Date Revision Changes 15-Mar-2006 1 Initial release.
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ST7540 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.